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![](/forums/images/ca_evo_db/misc/spacer.gif) | W9751G6KB DATASHEET | ![](/forums/images/ca_evo_db/misc/spacer.gif) |
Компонент | Описание | Производитель | PDF | Buy |
W9751G6KB | 8M 4 BANKS 16 BIT DDR2 SDRAM | Winbond | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
![](/forums/images/ca_evo_db/misc/spacer.gif) | *W97*: Расширенные результаты | ![](/forums/images/ca_evo_db/misc/spacer.gif) |
Компонент | Описание | Производитель | PDF | Buy |
BLW97 | HF power transistor | NXP Semiconductors | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
BLW97 | NPN SILICON RF POWER TRANSISTOR | Advanced Semiconductor | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
BPW97 | Silicon PIN Photodiode | Vishay Siliconix | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
BYW97 | Fast soft-recovery controlled avalanche rectifiers | NXP Semiconductors | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
BCW97 | Medium Power Amplifiers and Switches | List of Unclassifed Manufacturers | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
OXFW971 | 16 Channel Streaming Audio Firewire I/O Controller with Midi and S/PDIF | Oxford Semiconductor | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
W9712G6JB | 2M ‡ 4 BANKS ‡ 16 BIT DDR2 SDRAM | Winbond | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
W9712G8JB | 4M ‡ 4 BANKS ‡ 8 BIT DDR2 SDRAM | Winbond | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
W971GG6JB | 8M 8 BANKS 16 BIT DDR2 SDRAM | Winbond | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
W971GG6JB25I | DLL aligns DQ and DQS transitions with clock, Auto Refresh and Self Refresh modes, Write Data Mask | Winbond | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
W971GG8JB | 16M ‡ 8 BANKS ‡ 8 BIT DDR2 SDRAM | Winbond | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
W9725G6JB | 4M 4 BANKS 16 BIT DDR2 SDRAM | Winbond | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
W9725G6JB25I | Double Data Rate architecture: two data transfers per clock cycle | Winbond | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
W9725G6KB-25 | DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask | Winbond | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
W9725G6KB-3 | DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask | Winbond | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
W9725G6KB25A | DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask | Winbond | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
W9725G6KB25I | DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask | Winbond | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
W9725G6KB25K | DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask | Winbond | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
W9725G8JB | 8M 4 BANKS 8 BIT DDR2 SDRAM | Winbond | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
W972GG6JB | 16M 8 BANKS 16 BIT DDR2 SDRAM | Winbond | ![](/images/pdf_icon.png) | ![](/images/alisearch.png) |
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