[kison]

sl_64, Может так подойдет?

module div_f(clk, rst, k, out);

input clk, rst;
input [8:0] k;
output out;


reg [8:0] count; 
reg out;

always @(posedge clk)
  begin
    if((rst == 1) || (count == 0))
      begin
        count ‹= k;
        out ‹= ~rst;
      end
    else
    begin
      count ‹= count - 1;
      out ‹= 0;
    end
  end
endmodule

Для k=4, т.е. делим на 5