Static Timing Analysis

Project : GLCD
Build Time : 01/02/12 17:19:11
Device : CY8C5588AXI-060ES1
Temperature : -40C - 85C
Vio0 : 5.5
Vio1 : 5.5
Vio2 : 5.5
Vio3 : 5.5
Voltage : 5.5
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Type Nominal Frequency Required Frequency Maximum Frequency Violation
ClockBlock/clk_bus Async 24.000 MHz 24.000 MHz N/A
CyBUS_CLK Sync 24.000 MHz 24.000 MHz 42.088 MHz
CyILO Async 1.000 kHz 1.000 kHz N/A
CyIMO Async 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK Sync 24.000 MHz 24.000 MHz N/A
CyPLL_OUT Async 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer_Delay:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Delay:TimerUDB:sT16:timerdp:u1\/ci 42.088 MHz 23.760 17.907
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,2) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u0\ \Timer_Delay:TimerUDB:sT16:timerdp:u0\/clock \Timer_Delay:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer_Delay:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_Delay:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell2 U(0,3) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u1\ \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0i \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \Timer_Delay:TimerUDB:per_zero\ \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Delay:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.680
datapathcell1 U(0,2) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u0\ \Timer_Delay:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Timer_Delay:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer_Delay:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_Delay:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_Delay:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(0,3) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Delay:TimerUDB:sT16:timerdp:u1\/ci 44.783 MHz 22.330 19.337
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,3) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u1\ \Timer_Delay:TimerUDB:sT16:timerdp:u1\/clock \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
Route 1 \Timer_Delay:TimerUDB:per_zero\ \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Delay:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.680
datapathcell1 U(0,2) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u0\ \Timer_Delay:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Timer_Delay:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer_Delay:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_Delay:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_Delay:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(0,3) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer_Delay:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Delay:TimerUDB:sT16:timerdp:u0\/cs_addr_0 48.828 MHz 20.480 21.187
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,2) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u0\ \Timer_Delay:TimerUDB:sT16:timerdp:u0\/clock \Timer_Delay:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer_Delay:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_Delay:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell2 U(0,3) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u1\ \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0i \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \Timer_Delay:TimerUDB:per_zero\ \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Delay:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.680
datapathcell1 U(0,2) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer_Delay:TimerUDB:timer_enable\/q \Timer_Delay:TimerUDB:sT16:timerdp:u1\/ci 50.710 MHz 19.720 21.947
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,3) 1 \Timer_Delay:TimerUDB:timer_enable\ \Timer_Delay:TimerUDB:timer_enable\/clock_0 \Timer_Delay:TimerUDB:timer_enable\/q 1.250
Route 1 \Timer_Delay:TimerUDB:timer_enable\ \Timer_Delay:TimerUDB:timer_enable\/q \Timer_Delay:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.670
datapathcell1 U(0,2) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u0\ \Timer_Delay:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer_Delay:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer_Delay:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_Delay:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_Delay:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(0,3) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer_Delay:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Delay:TimerUDB:sT16:timerdp:u1\/cs_addr_0 51.114 MHz 19.564 22.103
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,2) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u0\ \Timer_Delay:TimerUDB:sT16:timerdp:u0\/clock \Timer_Delay:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer_Delay:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_Delay:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell2 U(0,3) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u1\ \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0i \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
datapathcell2 U(0,3) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u1\ \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Delay:TimerUDB:sT16:timerdp:u1\/cs_addr_0 2.764
datapathcell2 U(0,3) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Delay:TimerUDB:sT16:timerdp:u0\/cs_addr_0 52.493 MHz 19.050 22.617
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,3) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u1\ \Timer_Delay:TimerUDB:sT16:timerdp:u1\/clock \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
Route 1 \Timer_Delay:TimerUDB:per_zero\ \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Delay:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.680
datapathcell1 U(0,2) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Delay:TimerUDB:sT16:timerdp:u1\/cs_addr_0 55.145 MHz 18.134 23.533
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,3) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u1\ \Timer_Delay:TimerUDB:sT16:timerdp:u1\/clock \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
datapathcell2 U(0,3) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u1\ \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Delay:TimerUDB:sT16:timerdp:u1\/cs_addr_0 2.764
datapathcell2 U(0,3) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer_Delay:TimerUDB:timer_enable\/q \Timer_Delay:TimerUDB:sT16:timerdp:u0\/cs_addr_1 60.827 MHz 16.440 25.227
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,3) 1 \Timer_Delay:TimerUDB:timer_enable\ \Timer_Delay:TimerUDB:timer_enable\/clock_0 \Timer_Delay:TimerUDB:timer_enable\/q 1.250
Route 1 \Timer_Delay:TimerUDB:timer_enable\ \Timer_Delay:TimerUDB:timer_enable\/q \Timer_Delay:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.670
datapathcell1 U(0,2) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer_Delay:TimerUDB:timer_enable\/q \Timer_Delay:TimerUDB:sT16:timerdp:u1\/cs_addr_1 64.329 MHz 15.545 26.122
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,3) 1 \Timer_Delay:TimerUDB:timer_enable\ \Timer_Delay:TimerUDB:timer_enable\/clock_0 \Timer_Delay:TimerUDB:timer_enable\/q 1.250
Route 1 \Timer_Delay:TimerUDB:timer_enable\ \Timer_Delay:TimerUDB:timer_enable\/q \Timer_Delay:TimerUDB:sT16:timerdp:u1\/cs_addr_1 2.775
datapathcell2 U(0,3) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer_Delay:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Delay:TimerUDB:nrstSts:stsreg\/status_0 65.278 MHz 15.319 26.348
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,2) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u0\ \Timer_Delay:TimerUDB:sT16:timerdp:u0\/clock \Timer_Delay:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer_Delay:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_Delay:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell2 U(0,3) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u1\ \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0i \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \Timer_Delay:TimerUDB:per_zero\ \Timer_Delay:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Delay:TimerUDB:status_tc\/main_1 2.789
macrocell1 U(0,3) 1 \Timer_Delay:TimerUDB:status_tc\ \Timer_Delay:TimerUDB:status_tc\/main_1 \Timer_Delay:TimerUDB:status_tc\/q 3.350
Route 1 \Timer_Delay:TimerUDB:status_tc\ \Timer_Delay:TimerUDB:status_tc\/q \Timer_Delay:TimerUDB:nrstSts:stsreg\/status_0 2.330
statusicell1 U(0,3) 1 \Timer_Delay:TimerUDB:nrstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\Timer_Delay:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_Delay:TimerUDB:sT16:timerdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,2) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u0\ \Timer_Delay:TimerUDB:sT16:timerdp:u0\/clock \Timer_Delay:TimerUDB:sT16:timerdp:u0\/co_msb 3.210
Route 1 \Timer_Delay:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_Delay:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_Delay:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(0,3) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
ClockBlock_1k__SYNC/out \Timer_Delay:TimerUDB:sT16:timerdp:u0\/clk_en 3.291
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 ClockBlock_1k__SYNC ClockBlock_1k__SYNC/clock ClockBlock_1k__SYNC/out 1.000
Route 1 ClockBlock_1k__SYNC_OUT ClockBlock_1k__SYNC/out \Timer_Delay:TimerUDB:sT16:timerdp:u0\/clk_en 2.291
datapathcell1 U(0,2) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer_Delay:TimerUDB:trig_disable\/q \Timer_Delay:TimerUDB:timer_enable\/main_3 3.547
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,3) 1 \Timer_Delay:TimerUDB:trig_disable\ \Timer_Delay:TimerUDB:trig_disable\/clock_0 \Timer_Delay:TimerUDB:trig_disable\/q 1.250
Route 1 \Timer_Delay:TimerUDB:trig_disable\ \Timer_Delay:TimerUDB:trig_disable\/q \Timer_Delay:TimerUDB:timer_enable\/main_3 2.297
macrocell2 U(0,3) 1 \Timer_Delay:TimerUDB:timer_enable\ HOLD 0.000
Clock Skew 0.000
\Timer_Delay:TimerUDB:trig_disable\/q \Timer_Delay:TimerUDB:trig_disable\/main_3 3.547
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,3) 1 \Timer_Delay:TimerUDB:trig_disable\ \Timer_Delay:TimerUDB:trig_disable\/clock_0 \Timer_Delay:TimerUDB:trig_disable\/q 1.250
macrocell3 U(0,3) 1 \Timer_Delay:TimerUDB:trig_disable\ \Timer_Delay:TimerUDB:trig_disable\/q \Timer_Delay:TimerUDB:trig_disable\/main_3 2.297
macrocell3 U(0,3) 1 \Timer_Delay:TimerUDB:trig_disable\ HOLD 0.000
Clock Skew 0.000
\Timer_Delay:TimerUDB:timer_enable\/q \Timer_Delay:TimerUDB:sT16:timerdp:u1\/cs_addr_1 4.025
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,3) 1 \Timer_Delay:TimerUDB:timer_enable\ \Timer_Delay:TimerUDB:timer_enable\/clock_0 \Timer_Delay:TimerUDB:timer_enable\/q 1.250
Route 1 \Timer_Delay:TimerUDB:timer_enable\ \Timer_Delay:TimerUDB:timer_enable\/q \Timer_Delay:TimerUDB:sT16:timerdp:u1\/cs_addr_1 2.775
datapathcell2 U(0,3) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_Delay:TimerUDB:timer_enable\/q \Timer_Delay:TimerUDB:timer_enable\/main_1 4.029
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,3) 1 \Timer_Delay:TimerUDB:timer_enable\ \Timer_Delay:TimerUDB:timer_enable\/clock_0 \Timer_Delay:TimerUDB:timer_enable\/q 1.250
macrocell2 U(0,3) 1 \Timer_Delay:TimerUDB:timer_enable\ \Timer_Delay:TimerUDB:timer_enable\/q \Timer_Delay:TimerUDB:timer_enable\/main_1 2.779
macrocell2 U(0,3) 1 \Timer_Delay:TimerUDB:timer_enable\ HOLD 0.000
Clock Skew 0.000
\Timer_Delay:TimerUDB:timer_enable\/q \Timer_Delay:TimerUDB:trig_disable\/main_1 4.029
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,3) 1 \Timer_Delay:TimerUDB:timer_enable\ \Timer_Delay:TimerUDB:timer_enable\/clock_0 \Timer_Delay:TimerUDB:timer_enable\/q 1.250
Route 1 \Timer_Delay:TimerUDB:timer_enable\ \Timer_Delay:TimerUDB:timer_enable\/q \Timer_Delay:TimerUDB:trig_disable\/main_1 2.779
macrocell3 U(0,3) 1 \Timer_Delay:TimerUDB:trig_disable\ HOLD 0.000
Clock Skew 0.000
ClockBlock_1k__SYNC/out \Timer_Delay:TimerUDB:nrstSts:stsreg\/clk_en 4.218
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 ClockBlock_1k__SYNC ClockBlock_1k__SYNC/clock ClockBlock_1k__SYNC/out 1.000
Route 1 ClockBlock_1k__SYNC_OUT ClockBlock_1k__SYNC/out \Timer_Delay:TimerUDB:nrstSts:stsreg\/clk_en 3.218
statusicell1 U(0,3) 1 \Timer_Delay:TimerUDB:nrstSts:stsreg\ HOLD 0.000
Clock Skew 0.000
ClockBlock_1k__SYNC/out \Timer_Delay:TimerUDB:sT16:timerdp:u1\/clk_en 4.218
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 ClockBlock_1k__SYNC ClockBlock_1k__SYNC/clock ClockBlock_1k__SYNC/out 1.000
Route 1 ClockBlock_1k__SYNC_OUT ClockBlock_1k__SYNC/out \Timer_Delay:TimerUDB:sT16:timerdp:u1\/clk_en 3.218
datapathcell2 U(0,3) 1 \Timer_Delay:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
ClockBlock_1k__SYNC/out \Timer_Delay:TimerUDB:timer_enable\/clk_en 4.218
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 ClockBlock_1k__SYNC ClockBlock_1k__SYNC/clock ClockBlock_1k__SYNC/out 1.000
Route 1 ClockBlock_1k__SYNC_OUT ClockBlock_1k__SYNC/out \Timer_Delay:TimerUDB:timer_enable\/clk_en 3.218
macrocell2 U(0,3) 1 \Timer_Delay:TimerUDB:timer_enable\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\LCD_DATA:ctrl_reg\/control_7 LCDD(7)_PAD 28.035
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \LCD_DATA:ctrl_reg\ \LCD_DATA:ctrl_reg\/busclk \LCD_DATA:ctrl_reg\/control_7 2.580
Route 1 Net_41 \LCD_DATA:ctrl_reg\/control_7 LCDD(7)/pin_input 7.362
iocell13 P4[4] 1 LCDD(7) LCDD(7)/pin_input LCDD(7)/pad_out 18.093
Route 1 LCDD(7)_PAD LCDD(7)/pad_out LCDD(7)_PAD 0.000
Clock Clock path delay 0.000
\LCD_DATA:ctrl_reg\/control_6 LCDD(6)_PAD 27.182
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \LCD_DATA:ctrl_reg\ \LCD_DATA:ctrl_reg\/busclk \LCD_DATA:ctrl_reg\/control_6 2.580
Route 1 Net_40 \LCD_DATA:ctrl_reg\/control_6 LCDD(6)/pin_input 7.488
iocell12 P4[5] 1 LCDD(6) LCDD(6)/pin_input LCDD(6)/pad_out 17.114
Route 1 LCDD(6)_PAD LCDD(6)/pad_out LCDD(6)_PAD 0.000
Clock Clock path delay 0.000
\LCD_DATA:ctrl_reg\/control_4 LCDD(4)_PAD 26.125
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \LCD_DATA:ctrl_reg\ \LCD_DATA:ctrl_reg\/busclk \LCD_DATA:ctrl_reg\/control_4 2.580
Route 1 Net_38 \LCD_DATA:ctrl_reg\/control_4 LCDD(4)/pin_input 7.488
iocell10 P4[7] 1 LCDD(4) LCDD(4)/pin_input LCDD(4)/pad_out 16.057
Route 1 LCDD(4)_PAD LCDD(4)/pad_out LCDD(4)_PAD 0.000
Clock Clock path delay 0.000
\LCD_DATA:ctrl_reg\/control_5 LCDD(5)_PAD 25.931
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \LCD_DATA:ctrl_reg\ \LCD_DATA:ctrl_reg\/busclk \LCD_DATA:ctrl_reg\/control_5 2.580
Route 1 Net_39 \LCD_DATA:ctrl_reg\/control_5 LCDD(5)/pin_input 6.809
iocell11 P4[6] 1 LCDD(5) LCDD(5)/pin_input LCDD(5)/pad_out 16.542
Route 1 LCDD(5)_PAD LCDD(5)/pad_out LCDD(5)_PAD 0.000
Clock Clock path delay 0.000
\LCD_DATA:ctrl_reg\/control_3 LCDD(3)_PAD 25.129
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \LCD_DATA:ctrl_reg\ \LCD_DATA:ctrl_reg\/busclk \LCD_DATA:ctrl_reg\/control_3 2.580
Route 1 Net_36 \LCD_DATA:ctrl_reg\/control_3 LCDD(3)/pin_input 6.262
iocell9 P6[0] 1 LCDD(3) LCDD(3)/pin_input LCDD(3)/pad_out 16.287
Route 1 LCDD(3)_PAD LCDD(3)/pad_out LCDD(3)_PAD 0.000
Clock Clock path delay 0.000
\LCD_DATA:ctrl_reg\/control_1 LCDD(1)_PAD 24.822
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \LCD_DATA:ctrl_reg\ \LCD_DATA:ctrl_reg\/busclk \LCD_DATA:ctrl_reg\/control_1 2.580
Route 1 Net_34 \LCD_DATA:ctrl_reg\/control_1 LCDD(1)/pin_input 6.263
iocell7 P6[2] 1 LCDD(1) LCDD(1)/pin_input LCDD(1)/pad_out 15.979
Route 1 LCDD(1)_PAD LCDD(1)/pad_out LCDD(1)_PAD 0.000
Clock Clock path delay 0.000
\LCD_DATA:ctrl_reg\/control_2 LCDD(2)_PAD 24.721
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \LCD_DATA:ctrl_reg\ \LCD_DATA:ctrl_reg\/busclk \LCD_DATA:ctrl_reg\/control_2 2.580
Route 1 Net_35 \LCD_DATA:ctrl_reg\/control_2 LCDD(2)/pin_input 5.614
iocell8 P6[1] 1 LCDD(2) LCDD(2)/pin_input LCDD(2)/pad_out 16.527
Route 1 LCDD(2)_PAD LCDD(2)/pad_out LCDD(2)_PAD 0.000
Clock Clock path delay 0.000
\LCD_DATA:ctrl_reg\/control_0 LCDD(0)_PAD 24.452
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \LCD_DATA:ctrl_reg\ \LCD_DATA:ctrl_reg\/busclk \LCD_DATA:ctrl_reg\/control_0 2.580
Route 1 Net_37 \LCD_DATA:ctrl_reg\/control_0 LCDD(0)/pin_input 5.630
iocell6 P6[3] 1 LCDD(0) LCDD(0)/pin_input LCDD(0)/pad_out 16.242
Route 1 LCDD(0)_PAD LCDD(0)/pad_out LCDD(0)_PAD 0.000
Clock Clock path delay 0.000