\Counter:CounterUDB:prevCapture\/q |
\Counter:CounterUDB:sC32:counterdp:u3\/ci |
29.302 MHz |
34.127 |
7.540 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell6 |
U(3,2) |
1 |
\Counter:CounterUDB:prevCapture\ |
\Counter:CounterUDB:prevCapture\/clock_0 |
\Counter:CounterUDB:prevCapture\/q |
1.250 |
Route |
|
1 |
\Counter:CounterUDB:prevCapture\ |
\Counter:CounterUDB:prevCapture\/q |
\Counter:CounterUDB:hwCapture\/main_0 |
2.292 |
macrocell4 |
U(3,2) |
1 |
\Counter:CounterUDB:hwCapture\ |
\Counter:CounterUDB:hwCapture\/main_0 |
\Counter:CounterUDB:hwCapture\/q |
3.350 |
Route |
|
1 |
\Counter:CounterUDB:hwCapture\ |
\Counter:CounterUDB:hwCapture\/q |
\Counter:CounterUDB:sC32:counterdp:u0\/cs_addr_0 |
5.805 |
datapathcell1 |
U(2,3) |
1 |
\Counter:CounterUDB:sC32:counterdp:u0\ |
\Counter:CounterUDB:sC32:counterdp:u0\/cs_addr_0 |
\Counter:CounterUDB:sC32:counterdp:u0\/co_msb |
9.710 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u0.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u0\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u1\/ci |
0.000 |
datapathcell2 |
U(3,3) |
1 |
\Counter:CounterUDB:sC32:counterdp:u1\ |
\Counter:CounterUDB:sC32:counterdp:u1\/ci |
\Counter:CounterUDB:sC32:counterdp:u1\/co_msb |
3.310 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u1.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u1\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u2\/ci |
0.000 |
datapathcell3 |
U(3,2) |
1 |
\Counter:CounterUDB:sC32:counterdp:u2\ |
\Counter:CounterUDB:sC32:counterdp:u2\/ci |
\Counter:CounterUDB:sC32:counterdp:u2\/co_msb |
3.310 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u2.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u2\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u3\/ci |
0.000 |
datapathcell4 |
U(2,2) |
1 |
\Counter:CounterUDB:sC32:counterdp:u3\ |
|
SETUP |
5.100 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
\Counter:CounterUDB:sC32:counterdp:u3\/ci |
30.074 MHz |
33.251 |
8.416 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell1 |
U(3,2) |
1 |
\Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ |
\Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock |
\Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
2.580 |
Route |
|
1 |
\Counter:CounterUDB:control_7\ |
\Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
\Counter:CounterUDB:count_enable\/main_1 |
2.312 |
macrocell2 |
U(3,2) |
1 |
\Counter:CounterUDB:count_enable\ |
\Counter:CounterUDB:count_enable\/main_1 |
\Counter:CounterUDB:count_enable\/q |
3.350 |
Route |
|
1 |
\Counter:CounterUDB:count_enable\ |
\Counter:CounterUDB:count_enable\/q |
\Counter:CounterUDB:sC32:counterdp:u0\/cs_addr_1 |
3.579 |
datapathcell1 |
U(2,3) |
1 |
\Counter:CounterUDB:sC32:counterdp:u0\ |
\Counter:CounterUDB:sC32:counterdp:u0\/cs_addr_1 |
\Counter:CounterUDB:sC32:counterdp:u0\/co_msb |
9.710 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u0.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u0\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u1\/ci |
0.000 |
datapathcell2 |
U(3,3) |
1 |
\Counter:CounterUDB:sC32:counterdp:u1\ |
\Counter:CounterUDB:sC32:counterdp:u1\/ci |
\Counter:CounterUDB:sC32:counterdp:u1\/co_msb |
3.310 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u1.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u1\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u2\/ci |
0.000 |
datapathcell3 |
U(3,2) |
1 |
\Counter:CounterUDB:sC32:counterdp:u2\ |
\Counter:CounterUDB:sC32:counterdp:u2\/ci |
\Counter:CounterUDB:sC32:counterdp:u2\/co_msb |
3.310 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u2.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u2\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u3\/ci |
0.000 |
datapathcell4 |
U(2,2) |
1 |
\Counter:CounterUDB:sC32:counterdp:u3\ |
|
SETUP |
5.100 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\Counter:CounterUDB:count_stored_i\/q |
\Counter:CounterUDB:sC32:counterdp:u3\/ci |
31.352 MHz |
31.896 |
9.771 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell3 |
U(3,2) |
1 |
\Counter:CounterUDB:count_stored_i\ |
\Counter:CounterUDB:count_stored_i\/clock_0 |
\Counter:CounterUDB:count_stored_i\/q |
1.250 |
Route |
|
1 |
\Counter:CounterUDB:count_stored_i\ |
\Counter:CounterUDB:count_stored_i\/q |
\Counter:CounterUDB:count_enable\/main_2 |
2.287 |
macrocell2 |
U(3,2) |
1 |
\Counter:CounterUDB:count_enable\ |
\Counter:CounterUDB:count_enable\/main_2 |
\Counter:CounterUDB:count_enable\/q |
3.350 |
Route |
|
1 |
\Counter:CounterUDB:count_enable\ |
\Counter:CounterUDB:count_enable\/q |
\Counter:CounterUDB:sC32:counterdp:u0\/cs_addr_1 |
3.579 |
datapathcell1 |
U(2,3) |
1 |
\Counter:CounterUDB:sC32:counterdp:u0\ |
\Counter:CounterUDB:sC32:counterdp:u0\/cs_addr_1 |
\Counter:CounterUDB:sC32:counterdp:u0\/co_msb |
9.710 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u0.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u0\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u1\/ci |
0.000 |
datapathcell2 |
U(3,3) |
1 |
\Counter:CounterUDB:sC32:counterdp:u1\ |
\Counter:CounterUDB:sC32:counterdp:u1\/ci |
\Counter:CounterUDB:sC32:counterdp:u1\/co_msb |
3.310 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u1.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u1\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u2\/ci |
0.000 |
datapathcell3 |
U(3,2) |
1 |
\Counter:CounterUDB:sC32:counterdp:u2\ |
\Counter:CounterUDB:sC32:counterdp:u2\/ci |
\Counter:CounterUDB:sC32:counterdp:u2\/co_msb |
3.310 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u2.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u2\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u3\/ci |
0.000 |
datapathcell4 |
U(2,2) |
1 |
\Counter:CounterUDB:sC32:counterdp:u3\ |
|
SETUP |
5.100 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\Counter:CounterUDB:prevCapture\/q |
\Counter:CounterUDB:sC32:counterdp:u3\/ci |
32.449 MHz |
30.818 |
10.849 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell6 |
U(3,2) |
1 |
\Counter:CounterUDB:prevCapture\ |
\Counter:CounterUDB:prevCapture\/clock_0 |
\Counter:CounterUDB:prevCapture\/q |
1.250 |
Route |
|
1 |
\Counter:CounterUDB:prevCapture\ |
\Counter:CounterUDB:prevCapture\/q |
\Counter:CounterUDB:hwCapture\/main_0 |
2.292 |
macrocell4 |
U(3,2) |
1 |
\Counter:CounterUDB:hwCapture\ |
\Counter:CounterUDB:hwCapture\/main_0 |
\Counter:CounterUDB:hwCapture\/q |
3.350 |
Route |
|
1 |
\Counter:CounterUDB:hwCapture\ |
\Counter:CounterUDB:hwCapture\/q |
\Counter:CounterUDB:sC32:counterdp:u1\/cs_addr_0 |
5.806 |
datapathcell2 |
U(3,3) |
1 |
\Counter:CounterUDB:sC32:counterdp:u1\ |
\Counter:CounterUDB:sC32:counterdp:u1\/cs_addr_0 |
\Counter:CounterUDB:sC32:counterdp:u1\/co_msb |
9.710 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u1.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u1\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u2\/ci |
0.000 |
datapathcell3 |
U(3,2) |
1 |
\Counter:CounterUDB:sC32:counterdp:u2\ |
\Counter:CounterUDB:sC32:counterdp:u2\/ci |
\Counter:CounterUDB:sC32:counterdp:u2\/co_msb |
3.310 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u2.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u2\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u3\/ci |
0.000 |
datapathcell4 |
U(2,2) |
1 |
\Counter:CounterUDB:sC32:counterdp:u3\ |
|
SETUP |
5.100 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\Counter:CounterUDB:prevCapture\/q |
\Counter:CounterUDB:sC32:counterdp:u2\/ci |
32.450 MHz |
30.817 |
10.850 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell6 |
U(3,2) |
1 |
\Counter:CounterUDB:prevCapture\ |
\Counter:CounterUDB:prevCapture\/clock_0 |
\Counter:CounterUDB:prevCapture\/q |
1.250 |
Route |
|
1 |
\Counter:CounterUDB:prevCapture\ |
\Counter:CounterUDB:prevCapture\/q |
\Counter:CounterUDB:hwCapture\/main_0 |
2.292 |
macrocell4 |
U(3,2) |
1 |
\Counter:CounterUDB:hwCapture\ |
\Counter:CounterUDB:hwCapture\/main_0 |
\Counter:CounterUDB:hwCapture\/q |
3.350 |
Route |
|
1 |
\Counter:CounterUDB:hwCapture\ |
\Counter:CounterUDB:hwCapture\/q |
\Counter:CounterUDB:sC32:counterdp:u0\/cs_addr_0 |
5.805 |
datapathcell1 |
U(2,3) |
1 |
\Counter:CounterUDB:sC32:counterdp:u0\ |
\Counter:CounterUDB:sC32:counterdp:u0\/cs_addr_0 |
\Counter:CounterUDB:sC32:counterdp:u0\/co_msb |
9.710 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u0.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u0\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u1\/ci |
0.000 |
datapathcell2 |
U(3,3) |
1 |
\Counter:CounterUDB:sC32:counterdp:u1\ |
\Counter:CounterUDB:sC32:counterdp:u1\/ci |
\Counter:CounterUDB:sC32:counterdp:u1\/co_msb |
3.310 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u1.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u1\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u2\/ci |
0.000 |
datapathcell3 |
U(3,2) |
1 |
\Counter:CounterUDB:sC32:counterdp:u2\ |
|
SETUP |
5.100 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
\Counter:CounterUDB:sC32:counterdp:u3\/ci |
33.095 MHz |
30.216 |
11.451 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell1 |
U(3,2) |
1 |
\Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ |
\Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock |
\Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
2.580 |
Route |
|
1 |
\Counter:CounterUDB:control_7\ |
\Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
\Counter:CounterUDB:count_enable\/main_1 |
2.312 |
macrocell2 |
U(3,2) |
1 |
\Counter:CounterUDB:count_enable\ |
\Counter:CounterUDB:count_enable\/main_1 |
\Counter:CounterUDB:count_enable\/q |
3.350 |
Route |
|
1 |
\Counter:CounterUDB:count_enable\ |
\Counter:CounterUDB:count_enable\/q |
\Counter:CounterUDB:sC32:counterdp:u1\/cs_addr_1 |
3.854 |
datapathcell2 |
U(3,3) |
1 |
\Counter:CounterUDB:sC32:counterdp:u1\ |
\Counter:CounterUDB:sC32:counterdp:u1\/cs_addr_1 |
\Counter:CounterUDB:sC32:counterdp:u1\/co_msb |
9.710 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u1.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u1\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u2\/ci |
0.000 |
datapathcell3 |
U(3,2) |
1 |
\Counter:CounterUDB:sC32:counterdp:u2\ |
\Counter:CounterUDB:sC32:counterdp:u2\/ci |
\Counter:CounterUDB:sC32:counterdp:u2\/co_msb |
3.310 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u2.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u2\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u3\/ci |
0.000 |
datapathcell4 |
U(2,2) |
1 |
\Counter:CounterUDB:sC32:counterdp:u3\ |
|
SETUP |
5.100 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
\Counter:CounterUDB:sC32:counterdp:u2\/ci |
33.399 MHz |
29.941 |
11.726 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell1 |
U(3,2) |
1 |
\Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ |
\Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock |
\Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
2.580 |
Route |
|
1 |
\Counter:CounterUDB:control_7\ |
\Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
\Counter:CounterUDB:count_enable\/main_1 |
2.312 |
macrocell2 |
U(3,2) |
1 |
\Counter:CounterUDB:count_enable\ |
\Counter:CounterUDB:count_enable\/main_1 |
\Counter:CounterUDB:count_enable\/q |
3.350 |
Route |
|
1 |
\Counter:CounterUDB:count_enable\ |
\Counter:CounterUDB:count_enable\/q |
\Counter:CounterUDB:sC32:counterdp:u0\/cs_addr_1 |
3.579 |
datapathcell1 |
U(2,3) |
1 |
\Counter:CounterUDB:sC32:counterdp:u0\ |
\Counter:CounterUDB:sC32:counterdp:u0\/cs_addr_1 |
\Counter:CounterUDB:sC32:counterdp:u0\/co_msb |
9.710 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u0.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u0\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u1\/ci |
0.000 |
datapathcell2 |
U(3,3) |
1 |
\Counter:CounterUDB:sC32:counterdp:u1\ |
\Counter:CounterUDB:sC32:counterdp:u1\/ci |
\Counter:CounterUDB:sC32:counterdp:u1\/co_msb |
3.310 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u1.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u1\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u2\/ci |
0.000 |
datapathcell3 |
U(3,2) |
1 |
\Counter:CounterUDB:sC32:counterdp:u2\ |
|
SETUP |
5.100 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\Counter:CounterUDB:count_stored_i\/q |
\Counter:CounterUDB:sC32:counterdp:u3\/ci |
34.649 MHz |
28.861 |
12.806 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell3 |
U(3,2) |
1 |
\Counter:CounterUDB:count_stored_i\ |
\Counter:CounterUDB:count_stored_i\/clock_0 |
\Counter:CounterUDB:count_stored_i\/q |
1.250 |
Route |
|
1 |
\Counter:CounterUDB:count_stored_i\ |
\Counter:CounterUDB:count_stored_i\/q |
\Counter:CounterUDB:count_enable\/main_2 |
2.287 |
macrocell2 |
U(3,2) |
1 |
\Counter:CounterUDB:count_enable\ |
\Counter:CounterUDB:count_enable\/main_2 |
\Counter:CounterUDB:count_enable\/q |
3.350 |
Route |
|
1 |
\Counter:CounterUDB:count_enable\ |
\Counter:CounterUDB:count_enable\/q |
\Counter:CounterUDB:sC32:counterdp:u1\/cs_addr_1 |
3.854 |
datapathcell2 |
U(3,3) |
1 |
\Counter:CounterUDB:sC32:counterdp:u1\ |
\Counter:CounterUDB:sC32:counterdp:u1\/cs_addr_1 |
\Counter:CounterUDB:sC32:counterdp:u1\/co_msb |
9.710 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u1.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u1\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u2\/ci |
0.000 |
datapathcell3 |
U(3,2) |
1 |
\Counter:CounterUDB:sC32:counterdp:u2\ |
\Counter:CounterUDB:sC32:counterdp:u2\/ci |
\Counter:CounterUDB:sC32:counterdp:u2\/co_msb |
3.310 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u2.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u2\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u3\/ci |
0.000 |
datapathcell4 |
U(2,2) |
1 |
\Counter:CounterUDB:sC32:counterdp:u3\ |
|
SETUP |
5.100 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\Counter:CounterUDB:count_stored_i\/q |
\Counter:CounterUDB:sC32:counterdp:u2\/ci |
34.982 MHz |
28.586 |
13.081 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell3 |
U(3,2) |
1 |
\Counter:CounterUDB:count_stored_i\ |
\Counter:CounterUDB:count_stored_i\/clock_0 |
\Counter:CounterUDB:count_stored_i\/q |
1.250 |
Route |
|
1 |
\Counter:CounterUDB:count_stored_i\ |
\Counter:CounterUDB:count_stored_i\/q |
\Counter:CounterUDB:count_enable\/main_2 |
2.287 |
macrocell2 |
U(3,2) |
1 |
\Counter:CounterUDB:count_enable\ |
\Counter:CounterUDB:count_enable\/main_2 |
\Counter:CounterUDB:count_enable\/q |
3.350 |
Route |
|
1 |
\Counter:CounterUDB:count_enable\ |
\Counter:CounterUDB:count_enable\/q |
\Counter:CounterUDB:sC32:counterdp:u0\/cs_addr_1 |
3.579 |
datapathcell1 |
U(2,3) |
1 |
\Counter:CounterUDB:sC32:counterdp:u0\ |
\Counter:CounterUDB:sC32:counterdp:u0\/cs_addr_1 |
\Counter:CounterUDB:sC32:counterdp:u0\/co_msb |
9.710 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u0.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u0\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u1\/ci |
0.000 |
datapathcell2 |
U(3,3) |
1 |
\Counter:CounterUDB:sC32:counterdp:u1\ |
\Counter:CounterUDB:sC32:counterdp:u1\/ci |
\Counter:CounterUDB:sC32:counterdp:u1\/co_msb |
3.310 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u1.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u1\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u2\/ci |
0.000 |
datapathcell3 |
U(3,2) |
1 |
\Counter:CounterUDB:sC32:counterdp:u2\ |
|
SETUP |
5.100 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\Counter:CounterUDB:prevCapture\/q |
\Counter:CounterUDB:sC32:counterdp:u2\/ci |
36.353 MHz |
27.508 |
14.159 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell6 |
U(3,2) |
1 |
\Counter:CounterUDB:prevCapture\ |
\Counter:CounterUDB:prevCapture\/clock_0 |
\Counter:CounterUDB:prevCapture\/q |
1.250 |
Route |
|
1 |
\Counter:CounterUDB:prevCapture\ |
\Counter:CounterUDB:prevCapture\/q |
\Counter:CounterUDB:hwCapture\/main_0 |
2.292 |
macrocell4 |
U(3,2) |
1 |
\Counter:CounterUDB:hwCapture\ |
\Counter:CounterUDB:hwCapture\/main_0 |
\Counter:CounterUDB:hwCapture\/q |
3.350 |
Route |
|
1 |
\Counter:CounterUDB:hwCapture\ |
\Counter:CounterUDB:hwCapture\/q |
\Counter:CounterUDB:sC32:counterdp:u1\/cs_addr_0 |
5.806 |
datapathcell2 |
U(3,3) |
1 |
\Counter:CounterUDB:sC32:counterdp:u1\ |
\Counter:CounterUDB:sC32:counterdp:u1\/cs_addr_0 |
\Counter:CounterUDB:sC32:counterdp:u1\/co_msb |
9.710 |
Route |
|
1 |
\Counter:CounterUDB:sC32:counterdp:u1.co_msb__sig\ |
\Counter:CounterUDB:sC32:counterdp:u1\/co_msb |
\Counter:CounterUDB:sC32:counterdp:u2\/ci |
0.000 |
datapathcell3 |
U(3,2) |
1 |
\Counter:CounterUDB:sC32:counterdp:u2\ |
|
SETUP |
5.100 |
Clock |
|
|
|
|
Skew |
0.000 |
|