Static Timing Analysis

Project : 3_Phase_DMA_To_PWM_Generator
Build Time : 05/19/12 22:32:25
Device : CY8C3866AXI-040
Temperature : -40C - 85C
Vio0 : 5.0
Vio1 : 5.0
Vio2 : 5.0
Vio3 : 5.0
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Type Nominal Frequency Required Frequency Maximum Frequency Violation
ClockBlock/clk_bus Async 24.000 MHz 24.000 MHz N/A
ClockBlock/dclk_0 Async 4.000 MHz 4.000 MHz N/A
CyBUS_CLK Sync 24.000 MHz 24.000 MHz N/A
CyILO Async 1.000 kHz 1.000 kHz N/A
CyIMO Async 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK Sync 24.000 MHz 24.000 MHz N/A
CyPLL_OUT Async 24.000 MHz 24.000 MHz N/A
PWM_Clock Sync 4.000 MHz 4.000 MHz 56.641 MHz
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 250ns(4 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM_3:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_3:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 56.641 MHz 17.655 232.345
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,2) 1 \PWM_3:PWMUDB:sP8:pwmdp:u0\ \PWM_3:PWMUDB:sP8:pwmdp:u0\/clock \PWM_3:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
datapathcell3 U(2,2) 1 \PWM_3:PWMUDB:sP8:pwmdp:u0\ \PWM_3:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_3:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.285
datapathcell3 U(2,2) 1 \PWM_3:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 56.651 MHz 17.652 232.348
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
datapathcell1 U(1,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.282
datapathcell1 U(1,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 56.847 MHz 17.591 232.409
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/clock \PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
datapathcell2 U(1,0) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.221
datapathcell2 U(1,0) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_1:PWMUDB:final_kill_reg\/q \PWM_2:PWMUDB:sSTSReg:rstSts:stsreg\/status_5 64.516 MHz 15.500 234.500
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,1) 1 \PWM_1:PWMUDB:final_kill_reg\ \PWM_1:PWMUDB:final_kill_reg\/clock_0 \PWM_1:PWMUDB:final_kill_reg\/q 1.250
Route 1 \PWM_1:PWMUDB:final_kill_reg\ \PWM_1:PWMUDB:final_kill_reg\/q \PWM_1:PWMUDB:status_5\/main_0 2.295
macrocell8 U(2,1) 1 \PWM_1:PWMUDB:status_5\ \PWM_1:PWMUDB:status_5\/main_0 \PWM_1:PWMUDB:status_5\/q 3.350
Route 1 \PWM_1:PWMUDB:status_5\ \PWM_1:PWMUDB:status_5\/q \PWM_2:PWMUDB:sSTSReg:rstSts:stsreg\/status_5 7.035
statusicell2 U(1,0) 1 \PWM_2:PWMUDB:sSTSReg:rstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
\PWM_3:PWMUDB:runmode_enable\/q \PWM_3:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 66.348 MHz 15.072 234.928
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,2) 1 \PWM_3:PWMUDB:runmode_enable\ \PWM_3:PWMUDB:runmode_enable\/clock_0 \PWM_3:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_3:PWMUDB:runmode_enable\ \PWM_3:PWMUDB:runmode_enable\/q \PWM_3:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.302
datapathcell3 U(2,2) 1 \PWM_3:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 66.379 MHz 15.065 234.935
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,1) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.295
datapathcell1 U(1,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_2:PWMUDB:runmode_enable\/q \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 66.658 MHz 15.002 234.998
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,0) 1 \PWM_2:PWMUDB:runmode_enable\ \PWM_2:PWMUDB:runmode_enable\/clock_0 \PWM_2:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_2:PWMUDB:runmode_enable\ \PWM_2:PWMUDB:runmode_enable\/q \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.232
datapathcell2 U(1,0) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_1:PWMUDB:final_kill_reg\/q \PWM_1:PWMUDB:sSTSReg:rstSts:stsreg\/status_5 68.143 MHz 14.675 235.325
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,1) 1 \PWM_1:PWMUDB:final_kill_reg\ \PWM_1:PWMUDB:final_kill_reg\/clock_0 \PWM_1:PWMUDB:final_kill_reg\/q 1.250
Route 1 \PWM_1:PWMUDB:final_kill_reg\ \PWM_1:PWMUDB:final_kill_reg\/q \PWM_1:PWMUDB:status_5\/main_0 2.295
macrocell8 U(2,1) 1 \PWM_1:PWMUDB:status_5\ \PWM_1:PWMUDB:status_5\/main_0 \PWM_1:PWMUDB:status_5\/q 3.350
Route 1 \PWM_1:PWMUDB:status_5\ \PWM_1:PWMUDB:status_5\/q \PWM_1:PWMUDB:sSTSReg:rstSts:stsreg\/status_5 6.210
statusicell1 U(1,1) 1 \PWM_1:PWMUDB:sSTSReg:rstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
\PWM_1:PWMUDB:final_kill_reg\/q \PWM_3:PWMUDB:sSTSReg:rstSts:stsreg\/status_5 77.809 MHz 12.852 237.148
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,1) 1 \PWM_1:PWMUDB:final_kill_reg\ \PWM_1:PWMUDB:final_kill_reg\/clock_0 \PWM_1:PWMUDB:final_kill_reg\/q 1.250
Route 1 \PWM_1:PWMUDB:final_kill_reg\ \PWM_1:PWMUDB:final_kill_reg\/q \PWM_1:PWMUDB:status_5\/main_0 2.295
macrocell8 U(2,1) 1 \PWM_1:PWMUDB:status_5\ \PWM_1:PWMUDB:status_5\/main_0 \PWM_1:PWMUDB:status_5\/q 3.350
Route 1 \PWM_1:PWMUDB:status_5\ \PWM_1:PWMUDB:status_5\/q \PWM_3:PWMUDB:sSTSReg:rstSts:stsreg\/status_5 4.387
statusicell3 U(2,2) 1 \PWM_3:PWMUDB:sSTSReg:rstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
\PWM_3:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_67/main_1 87.002 MHz 11.494 238.506
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,2) 1 \PWM_3:PWMUDB:sP8:pwmdp:u0\ \PWM_3:PWMUDB:sP8:pwmdp:u0\/clock \PWM_3:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM_3:PWMUDB:cmp1_less\ \PWM_3:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_67/main_1 2.304
macrocell2 U(2,2) 1 Net_67 SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM_2:PWMUDB:status_0\/q \PWM_2:PWMUDB:sSTSReg:rstSts:stsreg\/status_0 1.510
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,0) 1 \PWM_2:PWMUDB:status_0\ \PWM_2:PWMUDB:status_0\/clock_0 \PWM_2:PWMUDB:status_0\/q 1.250
Route 1 \PWM_2:PWMUDB:status_0\ \PWM_2:PWMUDB:status_0\/q \PWM_2:PWMUDB:sSTSReg:rstSts:stsreg\/status_0 2.260
statusicell2 U(1,0) 1 \PWM_2:PWMUDB:sSTSReg:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_3:PWMUDB:status_0\/q \PWM_3:PWMUDB:sSTSReg:rstSts:stsreg\/status_0 1.564
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(2,2) 1 \PWM_3:PWMUDB:status_0\ \PWM_3:PWMUDB:status_0\/clock_0 \PWM_3:PWMUDB:status_0\/q 1.250
Route 1 \PWM_3:PWMUDB:status_0\ \PWM_3:PWMUDB:status_0\/q \PWM_3:PWMUDB:sSTSReg:rstSts:stsreg\/status_0 2.314
statusicell3 U(2,2) 1 \PWM_3:PWMUDB:sSTSReg:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:sSTSReg:rstSts:stsreg\/status_0 1.574
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(1,1) 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/clock_0 \PWM_1:PWMUDB:status_0\/q 1.250
Route 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:sSTSReg:rstSts:stsreg\/status_0 2.324
statusicell1 U(1,1) 1 \PWM_1:PWMUDB:sSTSReg:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_2:PWMUDB:prevCompare1\/q \PWM_2:PWMUDB:status_0\/main_2 3.473
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,0) 1 \PWM_2:PWMUDB:prevCompare1\ \PWM_2:PWMUDB:prevCompare1\/clock_0 \PWM_2:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_2:PWMUDB:prevCompare1\ \PWM_2:PWMUDB:prevCompare1\/q \PWM_2:PWMUDB:status_0\/main_2 2.223
macrocell11 U(1,0) 1 \PWM_2:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_2:PWMUDB:runmode_enable\/q \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.482
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,0) 1 \PWM_2:PWMUDB:runmode_enable\ \PWM_2:PWMUDB:runmode_enable\/clock_0 \PWM_2:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_2:PWMUDB:runmode_enable\ \PWM_2:PWMUDB:runmode_enable\/q \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.232
datapathcell2 U(1,0) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_2:PWMUDB:sSTSReg:rstSts:stsreg\/status_2 3.496
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/clock \PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.270
Route 1 \PWM_2:PWMUDB:tc_i\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_2:PWMUDB:sSTSReg:rstSts:stsreg\/status_2 2.226
statusicell2 U(1,0) 1 \PWM_2:PWMUDB:sSTSReg:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_2 3.536
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,1) 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/clock_0 \PWM_1:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_2 2.286
macrocell7 U(1,1) 1 \PWM_1:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_3:PWMUDB:prevCompare1\/q \PWM_3:PWMUDB:status_0\/main_2 3.538
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(2,2) 1 \PWM_3:PWMUDB:prevCompare1\ \PWM_3:PWMUDB:prevCompare1\/clock_0 \PWM_3:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_3:PWMUDB:prevCompare1\ \PWM_3:PWMUDB:prevCompare1\/q \PWM_3:PWMUDB:status_0\/main_2 2.288
macrocell14 U(2,2) 1 \PWM_3:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.545
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,1) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.295
datapathcell1 U(1,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_3:PWMUDB:runmode_enable\/q \PWM_3:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.552
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,2) 1 \PWM_3:PWMUDB:runmode_enable\ \PWM_3:PWMUDB:runmode_enable\/clock_0 \PWM_3:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_3:PWMUDB:runmode_enable\ \PWM_3:PWMUDB:runmode_enable\/q \PWM_3:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.302
datapathcell3 U(2,2) 1 \PWM_3:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ PWM_Clock
Source Destination Delay (ns)
Net_67/q C(0)_PAD 25.713
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(2,2) 1 Net_67 Net_67/clock_0 Net_67/q 1.250
Route 1 Net_67 Net_67/q C(0)/pin_input 8.263
iocell P2[7] 1 C(0) C(0)/pin_input C(0)/pad_out 16.200
Route 1 C(0)_PAD C(0)/pad_out C(0)_PAD 0.000
Clock Clock path delay 0.000
Net_53/q B(0)_PAD 23.975
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(1,0) 1 Net_53 Net_53/clock_0 Net_53/q 1.250
Route 1 Net_53 Net_53/q B(0)/pin_input 6.525
iocell P1[7] 1 B(0) B(0)/pin_input B(0)/pad_out 16.200
Route 1 B(0)_PAD B(0)/pad_out B(0)_PAD 0.000
Clock Clock path delay 0.000
Net_98/q A(0)_PAD 22.993
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,1) 1 Net_98 Net_98/clock_0 Net_98/q 1.250
Route 1 Net_98 Net_98/q A(0)/pin_input 5.543
iocell P1[6] 1 A(0) A(0)/pin_input A(0)/pad_out 16.200
Route 1 A(0)_PAD A(0)/pad_out A(0)_PAD 0.000
Clock Clock path delay 0.000