Static Timing Analysis

Project : PWM_3_Phase
Build Time : 05/20/12 17:26:51
Device : CY8C3866AXI-040
Temperature : -40C - 85C
Vio0 : 5.0
Vio1 : 5.0
Vio2 : 5.0
Vio3 : 5.0
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Type Nominal Frequency Required Frequency Maximum Frequency Violation
ClockBlock/clk_bus Async 24.000 MHz 24.000 MHz N/A
ClockBlock/dclk_0 Async 4.000 MHz 4.000 MHz N/A
Clock_1 Sync 4.000 MHz 4.000 MHz 56.641 MHz
CyBUS_CLK Sync 24.000 MHz 24.000 MHz N/A
CyILO Async 1.000 kHz 1.000 kHz N/A
CyIMO Async 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK Sync 24.000 MHz 24.000 MHz N/A
CyPLL_OUT Async 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 250ns(4 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 56.641 MHz 17.655 232.345
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
datapathcell1 U(0,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.285
datapathcell1 U(0,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 56.651 MHz 17.652 232.348
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,1) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/clock \PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
datapathcell2 U(1,1) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.282
datapathcell2 U(1,1) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_3:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_3:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 56.651 MHz 17.652 232.348
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(3,3) 1 \PWM_3:PWMUDB:sP8:pwmdp:u0\ \PWM_3:PWMUDB:sP8:pwmdp:u0\/clock \PWM_3:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
datapathcell3 U(3,3) 1 \PWM_3:PWMUDB:sP8:pwmdp:u0\ \PWM_3:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_3:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.282
datapathcell3 U(3,3) 1 \PWM_3:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_2:PWMUDB:runmode_enable\/q \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 66.322 MHz 15.078 234.922
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,1) 1 \PWM_2:PWMUDB:runmode_enable\ \PWM_2:PWMUDB:runmode_enable\/clock_0 \PWM_2:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_2:PWMUDB:runmode_enable\ \PWM_2:PWMUDB:runmode_enable\/q \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.308
datapathcell2 U(1,1) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 66.392 MHz 15.062 234.938
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,1) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.292
datapathcell1 U(0,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_3:PWMUDB:runmode_enable\/q \PWM_3:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 66.392 MHz 15.062 234.938
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,3) 1 \PWM_3:PWMUDB:runmode_enable\ \PWM_3:PWMUDB:runmode_enable\/clock_0 \PWM_3:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_3:PWMUDB:runmode_enable\ \PWM_3:PWMUDB:runmode_enable\/q \PWM_3:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.292
datapathcell3 U(3,3) 1 \PWM_3:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_135/main_1 86.949 MHz 11.501 238.499
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,1) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/clock \PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM_2:PWMUDB:cmp1_less\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_135/main_1 2.311
macrocell2 U(0,1) 1 Net_135 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_13/main_1 87.085 MHz 11.483 238.517
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_13/main_1 2.293
macrocell1 U(0,1) 1 Net_13 SETUP 3.510
Clock Skew 0.000
\PWM_3:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_195/main_1 87.108 MHz 11.480 238.520
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(3,3) 1 \PWM_3:PWMUDB:sP8:pwmdp:u0\ \PWM_3:PWMUDB:sP8:pwmdp:u0\/clock \PWM_3:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM_3:PWMUDB:cmp1_less\ \PWM_3:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_195/main_1 2.290
macrocell3 U(3,3) 1 Net_195 SETUP 3.510
Clock Skew 0.000
\PWM_2:PWMUDB:sP8:pwmdp:u0\/ce0_comb Net_135/main_2 91.912 MHz 10.880 239.120
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,1) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/clock \PWM_2:PWMUDB:sP8:pwmdp:u0\/ce0_comb 5.060
Route 1 \PWM_2:PWMUDB:cmp1_eq\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/ce0_comb Net_135/main_2 2.310
macrocell2 U(0,1) 1 Net_135 SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.542
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,1) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.292
datapathcell1 U(0,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_3:PWMUDB:runmode_enable\/q \PWM_3:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.542
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,3) 1 \PWM_3:PWMUDB:runmode_enable\ \PWM_3:PWMUDB:runmode_enable\/clock_0 \PWM_3:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_3:PWMUDB:runmode_enable\ \PWM_3:PWMUDB:runmode_enable\/q \PWM_3:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.292
datapathcell3 U(3,3) 1 \PWM_3:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_2:PWMUDB:runmode_enable\/q \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.558
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,1) 1 \PWM_2:PWMUDB:runmode_enable\ \PWM_2:PWMUDB:runmode_enable\/clock_0 \PWM_2:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_2:PWMUDB:runmode_enable\ \PWM_2:PWMUDB:runmode_enable\/q \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.308
datapathcell2 U(1,1) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_13/main_0 4.367
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,1) 1 \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \PWM_1:PWMUDB:ctrl_enable\ \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_13/main_0 2.327
macrocell1 U(0,1) 1 Net_13 HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 4.367
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,1) 1 \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \PWM_1:PWMUDB:ctrl_enable\ \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.327
macrocell4 U(0,1) 1 \PWM_1:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM_3:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_195/main_0 4.375
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,3) 1 \PWM_3:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \PWM_3:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \PWM_3:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \PWM_3:PWMUDB:ctrl_enable\ \PWM_3:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_195/main_0 2.335
macrocell3 U(3,3) 1 Net_195 HOLD 0.000
Clock Skew 0.000
\PWM_3:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \PWM_3:PWMUDB:runmode_enable\/main_0 4.375
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,3) 1 \PWM_3:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \PWM_3:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \PWM_3:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \PWM_3:PWMUDB:ctrl_enable\ \PWM_3:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \PWM_3:PWMUDB:runmode_enable\/main_0 2.335
macrocell6 U(3,3) 1 \PWM_3:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_135/main_0 4.376
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,1) 1 \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \PWM_2:PWMUDB:ctrl_enable\ \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_135/main_0 2.336
macrocell2 U(0,1) 1 Net_135 HOLD 0.000
Clock Skew 0.000
\PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \PWM_2:PWMUDB:runmode_enable\/main_0 4.376
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,1) 1 \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \PWM_2:PWMUDB:ctrl_enable\ \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \PWM_2:PWMUDB:runmode_enable\/main_0 2.336
macrocell5 U(0,1) 1 \PWM_2:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM_3:PWMUDB:sP8:pwmdp:u0\/ce0_comb Net_195/main_2 5.249
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(3,3) 1 \PWM_3:PWMUDB:sP8:pwmdp:u0\ \PWM_3:PWMUDB:sP8:pwmdp:u0\/clock \PWM_3:PWMUDB:sP8:pwmdp:u0\/ce0_comb 2.960
Route 1 \PWM_3:PWMUDB:cmp1_eq\ \PWM_3:PWMUDB:sP8:pwmdp:u0\/ce0_comb Net_195/main_2 2.289
macrocell3 U(3,3) 1 Net_195 HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_195/q Pin_1(0)_PAD 24.551
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(3,3) 1 Net_195 Net_195/clock_0 Net_195/q 1.250
Route 1 Net_195 Net_195/q Pin_1(0)/pin_input 6.301
sio P12[3] 1 Pin_1(0) Pin_1(0)/pin_input Pin_1(0)/pad_out 17.000
Route 1 Pin_1(0)_PAD Pin_1(0)/pad_out Pin_1(0)_PAD 0.000
Clock Clock path delay 0.000
Net_13/q A(0)_PAD 23.842
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,1) 1 Net_13 Net_13/clock_0 Net_13/q 1.250
Route 1 Net_13 Net_13/q A(0)/pin_input 6.392
iocell P1[6] 1 A(0) A(0)/pin_input A(0)/pad_out 16.200
Route 1 A(0)_PAD A(0)/pad_out A(0)_PAD 0.000
Clock Clock path delay 0.000
Net_135/q B(0)_PAD 23.021
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,1) 1 Net_135 Net_135/clock_0 Net_135/q 1.250
Route 1 Net_135 Net_135/q B(0)/pin_input 5.571
iocell P1[7] 1 B(0) B(0)/pin_input B(0)/pad_out 16.200
Route 1 B(0)_PAD B(0)/pad_out B(0)_PAD 0.000
Clock Clock path delay 0.000