Static Timing Analysis

Project : Impedance Calculator_v2
Build Time : 10/01/12 14:52:50
Device : CY8C3866AXI-040
Temperature : -40C - 85/125C
Vdda : 5.50
Vddd : 5.50
Vio0 : 5.50
Vio1 : 5.50
Vio2 : 5.50
Vio3 : 5.50
Voltage : 5.5
Vusb : 5.50
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_Clock_Ext(routed) ADC_Clock_Ext(routed) 2.640 MHz 2.640 MHz N/A
ADC_Ext_CP_Clk(routed) ADC_Ext_CP_Clk(routed) 5.077 MHz 5.077 MHz N/A
CyBUS_CLK(fixed-function) CyBUS_CLK(fixed-function) 66.000 MHz 66.000 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 66.000 MHz 66.000 MHz N/A
ADC_Clock_Ext CyMASTER_CLK 2.640 MHz 2.640 MHz 112.613 MHz
ADC_Ext_CP_Clk CyMASTER_CLK 5.077 MHz 5.077 MHz N/A
CyBUS_CLK CyMASTER_CLK 66.000 MHz 66.000 MHz 112.613 MHz
Sine_DMA/termout CyMASTER_CLK UNKNOWN UNKNOWN 105.731 MHz
CyPLL_OUT CyPLL_OUT 66.000 MHz 66.000 MHz N/A
CyXTAL CyXTAL 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 378.788ns(2.64 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
SOC_Signal/q Net_793/main_1 114.377 MHz 8.743 370.045
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,3) 1 SOC_Signal SOC_Signal/clock_0 SOC_Signal/q 1.250
Route 1 SOC_Signal SOC_Signal/q Net_793/main_1 3.983
macrocell7 U(0,3) 1 Net_793 SETUP 3.510
Clock Skew 0.000
SOC_Signal/q SOC_Signal/main_0 114.377 MHz 8.743 370.045
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,3) 1 SOC_Signal SOC_Signal/clock_0 SOC_Signal/q 1.250
macrocell8 U(0,3) 1 SOC_Signal SOC_Signal/q SOC_Signal/main_0 3.983
macrocell8 U(0,3) 1 SOC_Signal SETUP 3.510
Clock Skew 0.000
SOC_Signal/q Net_792/main_1 122.070 MHz 8.192 370.596
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,3) 1 SOC_Signal SOC_Signal/clock_0 SOC_Signal/q 1.250
Route 1 SOC_Signal SOC_Signal/q Net_792/main_1 3.432
macrocell6 U(0,3) 1 Net_792 SETUP 3.510
Clock Skew 0.000
\Sync_1:genblk1[0]:INST\/out Net_793/main_4 123.594 MHz 8.091 370.697
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,4) 1 \Sync_1:genblk1[0]:INST\ \Sync_1:genblk1[0]:INST\/clock \Sync_1:genblk1[0]:INST\/out 1.480
Route 1 Net_1144 \Sync_1:genblk1[0]:INST\/out Net_793/main_4 3.101
macrocell7 U(0,3) 1 Net_793 SETUP 3.510
Clock Skew 0.000
\Sync_1:genblk1[0]:INST\/out SOC_Signal/main_3 123.594 MHz 8.091 370.697
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,4) 1 \Sync_1:genblk1[0]:INST\ \Sync_1:genblk1[0]:INST\/clock \Sync_1:genblk1[0]:INST\/out 1.480
Route 1 Net_1144 \Sync_1:genblk1[0]:INST\/out SOC_Signal/main_3 3.101
macrocell8 U(0,3) 1 SOC_Signal SETUP 3.510
Clock Skew 0.000
\Sync_1:genblk1[0]:INST\/out Net_792/main_4 123.716 MHz 8.083 370.705
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,4) 1 \Sync_1:genblk1[0]:INST\ \Sync_1:genblk1[0]:INST\/clock \Sync_1:genblk1[0]:INST\/out 1.480
Route 1 Net_1144 \Sync_1:genblk1[0]:INST\/out Net_792/main_4 3.093
macrocell6 U(0,3) 1 Net_792 SETUP 3.510
Clock Skew 0.000
Net_793/q Net_793/main_2 132.450 MHz 7.550 371.238
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,3) 1 Net_793 Net_793/clock_0 Net_793/q 1.250
macrocell7 U(0,3) 1 Net_793 Net_793/q Net_793/main_2 2.790
macrocell7 U(0,3) 1 Net_793 SETUP 3.510
Clock Skew 0.000
Net_793/q SOC_Signal/main_1 132.450 MHz 7.550 371.238
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,3) 1 Net_793 Net_793/clock_0 Net_793/q 1.250
Route 1 Net_793 Net_793/q SOC_Signal/main_1 2.790
macrocell8 U(0,3) 1 SOC_Signal SETUP 3.510
Clock Skew 0.000
Net_793/q Net_792/main_2 132.521 MHz 7.546 371.242
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,3) 1 Net_793 Net_793/clock_0 Net_793/q 1.250
Route 1 Net_793 Net_793/q Net_792/main_2 2.786
macrocell6 U(0,3) 1 Net_792 SETUP 3.510
Clock Skew 0.000
Net_792/q Net_792/main_3 132.644 MHz 7.539 371.249
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,3) 1 Net_792 Net_792/clock_0 Net_792/q 1.250
macrocell6 U(0,3) 1 Net_792 Net_792/q Net_792/main_3 2.779
macrocell6 U(0,3) 1 Net_792 SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 15.1515ns(66 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SOC_Go:ctrl_reg\/control_0 Net_792/main_0 112.613 MHz 8.880 6.272
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,3) 1 \SOC_Go:ctrl_reg\ \SOC_Go:ctrl_reg\/clock \SOC_Go:ctrl_reg\/control_0 2.580
Route 1 Net_814 \SOC_Go:ctrl_reg\/control_0 Net_792/main_0 2.790
macrocell6 U(0,3) 1 Net_792 SETUP 3.510
Clock Skew 0.000
\SOC_Go:ctrl_reg\/control_0 Net_793/main_0 112.663 MHz 8.876 6.276
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,3) 1 \SOC_Go:ctrl_reg\ \SOC_Go:ctrl_reg\/clock \SOC_Go:ctrl_reg\/control_0 2.580
Route 1 Net_814 \SOC_Go:ctrl_reg\/control_0 Net_793/main_0 2.786
macrocell7 U(0,3) 1 Net_793 SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 30.303ns
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_526/q Net_125/main_0 105.731 MHz 9.458
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,4) 1 Net_526 Net_526/clock_0 Net_526/q 1.250
Route 1 Net_526 Net_526/q Net_125/main_0 4.698
macrocell4 U(0,4) 1 Net_125 SETUP 3.510
Clock Skew 0.000
Net_119/q Net_526/main_0 141.864 MHz 7.049
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,4) 1 Net_119 Net_119/clock_0 Net_119/q 1.250
Route 1 Net_119 Net_119/q Net_526/main_0 2.289
macrocell5 U(0,4) 1 Net_526 SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Net_792/q Net_793/main_3 4.025
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,3) 1 Net_792 Net_792/clock_0 Net_792/q 1.250
Route 1 Net_792 Net_792/q Net_793/main_3 2.775
macrocell7 U(0,3) 1 Net_793 HOLD 0.000
Clock Skew 0.000
Net_792/q SOC_Signal/main_2 4.025
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,3) 1 Net_792 Net_792/clock_0 Net_792/q 1.250
Route 1 Net_792 Net_792/q SOC_Signal/main_2 2.775
macrocell8 U(0,3) 1 SOC_Signal HOLD 0.000
Clock Skew 0.000
Net_792/q Net_792/main_3 4.029
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,3) 1 Net_792 Net_792/clock_0 Net_792/q 1.250
macrocell6 U(0,3) 1 Net_792 Net_792/q Net_792/main_3 2.779
macrocell6 U(0,3) 1 Net_792 HOLD 0.000
Clock Skew 0.000
Net_793/q Net_792/main_2 4.036
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,3) 1 Net_793 Net_793/clock_0 Net_793/q 1.250
Route 1 Net_793 Net_793/q Net_792/main_2 2.786
macrocell6 U(0,3) 1 Net_792 HOLD 0.000
Clock Skew 0.000
Net_793/q Net_793/main_2 4.040
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,3) 1 Net_793 Net_793/clock_0 Net_793/q 1.250
macrocell7 U(0,3) 1 Net_793 Net_793/q Net_793/main_2 2.790
macrocell7 U(0,3) 1 Net_793 HOLD 0.000
Clock Skew 0.000
Net_793/q SOC_Signal/main_1 4.040
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,3) 1 Net_793 Net_793/clock_0 Net_793/q 1.250
Route 1 Net_793 Net_793/q SOC_Signal/main_1 2.790
macrocell8 U(0,3) 1 SOC_Signal HOLD 0.000
Clock Skew 0.000
\Sync_1:genblk1[0]:INST\/out Net_792/main_4 4.093
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,4) 1 \Sync_1:genblk1[0]:INST\ \Sync_1:genblk1[0]:INST\/clock \Sync_1:genblk1[0]:INST\/out 1.000
Route 1 Net_1144 \Sync_1:genblk1[0]:INST\/out Net_792/main_4 3.093
macrocell6 U(0,3) 1 Net_792 HOLD 0.000
Clock Skew 0.000
\Sync_1:genblk1[0]:INST\/out Net_793/main_4 4.101
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,4) 1 \Sync_1:genblk1[0]:INST\ \Sync_1:genblk1[0]:INST\/clock \Sync_1:genblk1[0]:INST\/out 1.000
Route 1 Net_1144 \Sync_1:genblk1[0]:INST\/out Net_793/main_4 3.101
macrocell7 U(0,3) 1 Net_793 HOLD 0.000
Clock Skew 0.000
\Sync_1:genblk1[0]:INST\/out SOC_Signal/main_3 4.101
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,4) 1 \Sync_1:genblk1[0]:INST\ \Sync_1:genblk1[0]:INST\/clock \Sync_1:genblk1[0]:INST\/out 1.000
Route 1 Net_1144 \Sync_1:genblk1[0]:INST\/out SOC_Signal/main_3 3.101
macrocell8 U(0,3) 1 SOC_Signal HOLD 0.000
Clock Skew 0.000
SOC_Signal/q Net_792/main_1 4.682
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,3) 1 SOC_Signal SOC_Signal/clock_0 SOC_Signal/q 1.250
Route 1 SOC_Signal SOC_Signal/q Net_792/main_1 3.432
macrocell6 U(0,3) 1 Net_792 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SOC_Go:ctrl_reg\/control_0 Net_793/main_0 4.826
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,3) 1 \SOC_Go:ctrl_reg\ \SOC_Go:ctrl_reg\/clock \SOC_Go:ctrl_reg\/control_0 2.040
Route 1 Net_814 \SOC_Go:ctrl_reg\/control_0 Net_793/main_0 2.786
macrocell7 U(0,3) 1 Net_793 HOLD 0.000
Clock Skew 0.000
\SOC_Go:ctrl_reg\/control_0 Net_792/main_0 4.830
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,3) 1 \SOC_Go:ctrl_reg\ \SOC_Go:ctrl_reg\/clock \SOC_Go:ctrl_reg\/control_0 2.040
Route 1 Net_814 \SOC_Go:ctrl_reg\/control_0 Net_792/main_0 2.790
macrocell6 U(0,3) 1 Net_792 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Net_119/q Net_526/main_0 3.539
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,4) 1 Net_119 Net_119/clock_0 Net_119/q 1.250
Route 1 Net_119 Net_119/q Net_526/main_0 2.289
macrocell5 U(0,4) 1 Net_526 HOLD 0.000
Clock Skew 0.000
Net_526/q Net_125/main_0 5.948
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,4) 1 Net_526 Net_526/clock_0 Net_526/q 1.250
Route 1 Net_526 Net_526/q Net_125/main_0 4.698
macrocell4 U(0,4) 1 Net_125 HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ ADC_Clock_Ext
Source Destination Delay (ns)
SOC_Signal/q Trigger(0)_PAD 26.649
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,3) 1 SOC_Signal SOC_Signal/clock_0 SOC_Signal/q 1.250
Route 1 SOC_Signal SOC_Signal/q Trigger(0)/pin_input 8.399
sio P12[6] 1 Trigger(0) Trigger(0)/pin_input Trigger(0)/pad_out 17.000
Route 1 Trigger(0)_PAD Trigger(0)/pad_out Trigger(0)_PAD 0.000
Clock Clock path delay 0.000
+ Sine_DMA/termout
Source Destination Delay (ns)
Net_526/q InPhase_Clock(0)_PAD 42.049
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,4) 1 Net_526 Net_526/clock_0 Net_526/q 1.250
Route 1 Net_526 Net_526/q InPhase_Clock(0)/pin_input 8.346
sio P12[4] 1 InPhase_Clock(0) InPhase_Clock(0)/pin_input InPhase_Clock(0)/pad_out 17.000
Route 1 InPhase_Clock(0)_PAD InPhase_Clock(0)/pad_out InPhase_Clock(0)_PAD 0.000
Clock Clock path delay 15.453
Net_125/q Quadrature_Clock(0)_PAD 40.425
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,4) 1 Net_125 Net_125/clock_0 Net_125/q 1.250
Route 1 Net_125 Net_125/q Quadrature_Clock(0)/pin_input 6.722
sio P12[5] 1 Quadrature_Clock(0) Quadrature_Clock(0)/pin_input Quadrature_Clock(0)/pad_out 17.000
Route 1 Quadrature_Clock(0)_PAD Quadrature_Clock(0)/pad_out Quadrature_Clock(0)_PAD 0.000
Clock Clock path delay 15.453