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//////////////////////////////////////////////////////////////////////// // 文件名 :INIT.c // 文件功能 :系统初始化模块 // 作者 :xyliu // 创建时间 :2003年08月15日 // 处理器 :EPSON S1C33301 // 项目名称 :LYT V2 // 备注 : // //////////////////////////////////////////////////////////////////////// // 历史记录: // 编号 日期 作者 备注 // 0 2003-08-15 xyliu //////////////////////////////////////////////////////////////////////// //System Config //#include "..\Config\Config.h" //System include file #include "..\include\bcu.h" #include "..\include\idma.h" #include "..\include\int.h" #include "..\include\io.h" #include "..\include\presc.h" #include "..\include\8timer.h" #include "..\include\Init.h" /* Global variable define */ void _init_bcu(void) { // [0x4812E] bus control register setting: BCLK output enable; Burst ROM burst length is 8; // external interface method is #BSL system; #WAIT pin enable. *(volatile unsigned short *)BCU_SWAITE_ADDR = BCU_RBCLK_ENA | BCU_RBST8_8 | BCU_SBUSST_BSL | BCU_SWAITE_ENA; // [0x48130] DRAM timing setup register setting: CEFUNC1 = '1' CEFUNC0 = 'x'. *(volatile unsigned short *)BCU_RASC_ADDR = BCU_CEFUNC_COM; // [48120] Areas 15-18 setup register setting: (15 and 16 )Device size 16 bits, Output disable delay 0.5, Wait control 2. //*(volatile unsigned short *)BCU_A15_A18_ADDR = BCU_SZH_16 | BCU_DFH_05 | BCU_WTH_3; // [0x48122] Areas 13-14 setup register setting: device size 16 bits ,Output disable delay 2.5,Wait control 2. //System SRAM *(volatile unsigned short *)BCU_A13_A14_ADDR = BCU_SZL_16 | BCU_DFL_05 | BCU_WTL_1; // [0x48124] Areas 11-12( 0x1000000~0x17FFFFF; 0x1800000~1FFFFFF ) setup register setting: device size 16 bits ,Output disable delay 2.5,Wait control 2. //*(volatile unsigned short *)BCU_A11_A12_ADDR = BCU_SZL_16 | BCU_DFL_25 | BCU_WTL_2; // [0x48126] Area 9-10 setup register setting: device size 16 bits, output disable delay 0.5, wait control 2 //System Flash *(volatile unsigned short *)BCU_A9_A10_ADDR = BCU_SZL_16 | BCU_DFL_05 | BCU_WTL_2; // [0x48126] Area 9-10 setup register setting: device size 16 bits, output disable delay 0.5, wait control 2, area 9,10 use burst mode, burst wait cycle is 1 //*(volatile unsigned short *)BCU_A9_A10_ADDR = BCU_SZL_16 | BCU_DFL_05 | BCU_WTL_1 | BCU_BROH_USE | BCU_BROL_USE | BCU_BW_0; // [0x48128] Area 7-8( 0x400000~0x5FFFFF; 0x600000~0x7FFFFF ) setup register setting: Device size 16 bits, output disable delay 3.5, wait control 7, DRAM is not used in area 8 *(volatile unsigned short *)BCU_A7_A8_ADDR = BCU_DRAH_NOT | BCU_DRAL_NOT | BCU_SZL_16 | BCU_DFL_05 | BCU_WTL_0; // [0x4812A] Area 4-6 setup register setting: Device size 16 bits, output disable delay 3.5, wait control 7 in area 4,5,6 *(volatile unsigned short *)BCU_A4_A5_A6_ADDR = BCU_DFH_35 | BCU_WTH_7 | BCU_SZL_16 | BCU_DFL_35 | BCU_WTL_7; // [4813A] BCLK select register setting: area1 access speed is 2 cycles when use x2speed mode, BCLK output PLL CLK *(volatile unsigned short *)BCU_BCLKSEL_ADDR = BCU_BCLKSEL_PLL | BCU_A1X1MD; *(volatile unsigned short *)(0x48132) |= 0x0200; //Area 6 is internal *(volatile unsigned short *)(0x48132) &= 0xFFFD; //Area 6 is internal *(volatile unsigned short *)(0x4812A) &= 0x00ff; //Area 6 is internal *(volatile unsigned short *)(0x4812A) |= 0x01ff; //Area 6 is internal } /******************************************************************************* * _init_int * Type : void * Ret val : none * Argument : void * Function : Initialize interrupt controller. *******************************************************************************/ void _init_int(void) { // Disable all interrupt enable register *(volatile unsigned char *)INT_EP0_EK_ADDR = INT_ENABLE_DIS; *(volatile unsigned char *)INT_EHDM_EIDM_ADDR = INT_ENABLE_DIS; *(volatile unsigned char *)INT_E16T0_E16T1_ADDR = INT_ENABLE_DIS; *(volatile unsigned char *)INT_E16T2_E16T3_ADDR = INT_ENABLE_DIS; *(volatile unsigned char *)INT_E16T4_E16T5_ADDR = INT_ENABLE_DIS; *(volatile unsigned char *)INT_E8TU_ADDR = INT_ENABLE_DIS; *(volatile unsigned char *)INT_ES_ADDR = INT_ENABLE_DIS; *(volatile unsigned char *)INT_EADE_ECTM_EP4_ADDR = INT_ENABLE_DIS; // Reset all interrupt cause flag register (interrupt factor flag reset is read only mode) *(volatile unsigned char *)INT_FP0_FK_ADDR = INT_FLAG_RST; *(volatile unsigned char *)INT_FHDM_FIDM_ADDR = INT_FLAG_RST; *(volatile unsigned char *)INT_F16T0_F16T1_ADDR = INT_FLAG_RST; *(volatile unsigned char *)INT_F16T2_F16T3_ADDR = INT_FLAG_RST; *(volatile unsigned char *)INT_F16T4_F16T5_ADDR = INT_FLAG_RST; *(volatile unsigned char *)INT_F8TU_ADDR = INT_FLAG_RST; *(volatile unsigned char *)INT_FS_ADDR = INT_FLAG_RST; *(volatile unsigned char *)INT_FADE_FCTM_FP4_ADDR = INT_FLAG_RST; // Set all interrupt IDMA request register CPU request disable *(volatile unsigned char *)INT_RP0_RHDM_R16T0_ADDR = INT_RIDMA_DIS; *(volatile unsigned char *)INT_R16T1_R16T4_ADDR = INT_RIDMA_DIS; *(volatile unsigned char *)INT_R16T5_R8TU_RS0_ADDR = INT_RIDMA_DIS; *(volatile unsigned char *)INT_RS1_RADE_RP4_ADDR = INT_RIDMA_DIS; // Set all IDMA disable *(volatile unsigned char *)IDMA_DEP0_DEHDM_DE16T0_ADDR = IDMA_DEIDMA_DIS; *(volatile unsigned char *)IDMA_DE16T1_DE16T4_ADDR = IDMA_DEIDMA_DIS; *(volatile unsigned char *)IDMA_DE16T5_DE8TU_DES0_ADDR = IDMA_DEIDMA_DIS; *(volatile unsigned char *)IDMA_DES1_DEADE_DEP4_ADDR = IDMA_DEIDMA_DIS; }