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READ MEMORY [FOH]
The Read Memory command is used to read data from the 1024-bit EEPROM data field. The bus master follows the command byte with a two-byte address (TA1=(T7: TO), TA2=(T15:T
) that indicates a starting byte location within the data field. An 8-bit CRC of the command byte and address bytes is computed by the K1446VG5 and read back by the bus master to confirm that the correct command word and starting address were received. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus master is correct, the bus master issues read time slots and receives data from the K1446VG5 starting at the initial address and continuing until the end of the 1024-bit data field is reached or until a Reset Pulse is issued. If reading occurs through the end of memory space, the bus master may issue eight additional read time slots and the K1446VG5 will respond with a 8-bit CRC of all data bytes read from the initial starting byte through the last byte of memory. After the CRC is received by the bus master, any subsequent read time slots will appear as logical 1s until a Reset Pulse is issued. Any reads ended by a Reset Pulse prior to reaching the end of memory will not have the 8-bit CRC available. Typically a 16-bit CRC would be stored with each page of data to insure rapid, error-free data transfers that eliminate having to read a page multiple times to deter-mine if the received data is correct or not. If CRC values are imbedded within the data, a Reset Pulse may be issued at the end of memory space during a Read Memory command.
READ MEMORY [F0h]
The Read Memory command is used to read data from the 1024-bit EPROM data field. The bus master
follows the command byte with a 2-byte address (TA1=(T7:T0), TA2=(T15:T
) that indicates a starting
byte location within the data field. An 8–bit CRC of the command byte and address bytes is computed by
the DS1982 and read back by the bus master to confirm that the correct command word and starting
address were received. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and
the entire sequence must be repeated. If the CRC received by the bus master is correct, the bus master
issues read time slots and receives data from the DS1982 starting at the initial address and continuing
until the end of the 1024-bit data field is reached or until a Reset Pulse is issued. If reading occurs
through the end of memory space, the bus master may issue eight additional read time slots and the
DS1982 will respond with an 8-bit CRC of all data bytes read from the initial starting byte through the
last byte of memory. After the CRC is received by the bus master, any subsequent read time slots will
appear as logical 1s until a Reset Pulse is issued. Any reads ended by a Reset Pulse prior to reaching the
end of memory will not have the 8-bit CRC available.
Typically a 16-bit CRC would be stored with each page of data to ensure rapid, error-free data transfers
that eliminate having to read a page multiple times to determine if the received data is correct or not. (See
Book of DS19xx iButton Standards, Chapter 7 for the recommended file structure to be used with the
1-Wire environment.) If CRC values are imbedded within the data, a Reset Pulse may be issued at the end
of memory space during a Read Memory command.
Re: Простой копировщик домофонных ключей
