Сообщение от _Cahes_
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Я привык - что блокировка обозначается: "SD", или типа того
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ты даташит как буратино чтоль рассматриваешь? на предмет картинок....
читать не пробовал? хотя мне и по картинке ясно.
на вот просвещайся
гугль перевод в помощь.
Fault Detection
Converter protection from adverse operating conditions
can be implemented with proper
use of the Fault Comparator
and Latch blocks that are illustrated in Figure 20. The Fault
Comparator has an input threshold of 1.0 V and when
exceeded, sets the Fault Latch and generates two logic
signals
that simultaneously disable the primary control path.
The signal line labeled “Fault” connects directly to two gates
that control the output drivers. This direct path reduces the
driver turn−off propagation delay to approximately 70 ns.
The Fault Latch output is OR’ed with the UVLO output that
is derived from the V
ref
UVLO comparator, to produce the
logic output labeled “UVLO+Fault”. This signal disables
the Oscillator and the One−Shot by forcing both the C
OSC
and C
T
capacitors to be continually charged.
The Fault Latch is automatically reset during startup by a
logic “1” that appears at the V
ref
UVLO comparator output.
The latch can also be reset after startup by momentarily
pulling the Enable/UVLO Adjust pin low to disable the
Reference. Note that after activation, the Fault Latch will
remain in a set state only as long as V
CC
is provided to the
MC34067.
Also, Drive Output B will assume a high state if
the Fault input signal drops below the 1.0 V threshold level
even
after the Fault Latch has been set. In some applications
this characteristic could be problematic but it can be easily
remedied by AC coupling Drive Output B