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Defines | |
#define | Is_ext_reset() ((MCUSR&(1<<EXTRF)) ? TRUE:FALSE) |
#define | Ack_ext_reset() (MCUSR= ~(1<<EXTRF)) |
#define | Is_POR_reset() ((MCUSR&(1<<(MCUSR= ~(1<<PORF)))) ? TRUE:FALSE) |
#define | Ack_POR_reset() (MCUSR= ~(1<<PORF)) |
#define | Is_BOD_reset() ((MCUSR&(1<<BORF)) ? TRUE:FALSE) |
#define | Ack_BOD_reset() (MCUSR= ~(1<<BORF)) |
#define | Is_wdt_reset() ((MCUSR&(1<<WDRF)) ? TRUE:FALSE) |
#define | Ack_wdt_reset() (MCUSR= ~(1<<WDRF)) |
#define | Wdt_reset_instruction() (__watchdog_reset()) |
#define | Wdt_clear_flag() (Ack_wdt_reset()) |
#define | Wdt_change_enable() (WDTCSR |= (1<<WDCE) | (1<<WDE)) |
#define | Wdt_enable_16ms() (WDTCSR = (1<<WDE)) |
#define | Wdt_enable_32ms() (WDTCSR = (1<<WDE) | (1<<WDP0) ) |
#define | Wdt_enable_64ms() (WDTCSR = (1<<WDE) | (1<<WDP1) ) |
#define | Wdt_enable_125ms() (WDTCSR = (1<<WDE) | (1<<WDP1) | (1<<WDP0)) |
#define | Wdt_enable_250ms() (WDTCSR = (1<<WDE) | (1<<WDP2) ) |
#define | Wdt_enable_500ms() (WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0)) |
#define | Wdt_enable_1s() (WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP1)) |
#define | Wdt_enable_2s() (WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP1) | (1<<WDP0)) |
#define | Wdt_enable_4s() (WDTCSR = (1<<WDE) | (1<<WDP3) | (1<<WDP0)) |
#define | Wdt_enable_8s() (WDTCSR = (1<<WDE) | (1<<WDP3) | (1<<WDP1)) |
#define | Wdt_interrupt_16ms() (WDTCSR = (1<<WDIE)) |
#define | Wdt_interrupt_32ms() (WDTCSR = (1<<WDIE) | (1<<WDP0) ) |
#define | Wdt_interrupt_64ms() (WDTCSR = (1<<WDIE) | (1<<WDP1) ) |
#define | Wdt_interrupt_125ms() (WDTCSR = (1<<WDIE) | (1<<WDP1) | (1<<WDP0)) |
#define | Wdt_interrupt_250ms() (WDTCSR = (1<<WDIE) | (1<<WDP2) ) |
#define | Wdt_interrupt_500ms() (WDTCSR = (1<<WDIE) | (1<<WDP2) | (1<<WDP0)) |
#define | Wdt_interrupt_1s() (WDTCSR = (1<<WDIE) | (1<<WDP2) | (1<<WDP1)) |
#define | Wdt_interrupt_2s() (WDTCSR = (1<<WDIE) | (1<<WDP2) | (1<<WDP1) | (1<<WDP0)) |
#define | Wdt_interrupt_4s() (WDTCSR = (1<<WDIE) | (1<<WDP3) | (1<<WDP0)) |
#define | Wdt_interrupt_8s() (WDTCSR = (1<<WDIE) | (1<<WDP3) | (1<<WDP1)) |
#define | Wdt_enable_reserved5() (WDTCSR = (1<<WDE) | (1<<WDP3) | (1<<WDP2) | (1<<WDP1) | (1<<WDP0)) |
#define | Wdt_stop() (WDTCSR = 0x00) |
#define | Wdt_ack_interrupt() (WDTCSR = ~(1<<WDIF)) |
#define | Wdt_off() |
Wdt_off. | |
#define | Wdt_change_16ms() |
wdt_change_16ms. | |
#define | Wdt_change_32ms() |
wdt_change_32ms. | |
#define | Wdt_change_64ms() |
wdt_change_64ms. | |
#define | Wdt_change_125ms() |
wdt_change_32ms. | |
#define | Wdt_change_250ms() |
wdt_change_250ms. | |
#define | Wdt_change_500ms() |
wdt_change_500ms. | |
#define | Wdt_change_1s() |
wdt_change_1s. | |
#define | Wdt_change_2s() |
wdt_change_2s. | |
#define | Wdt_change_4s() |
wdt_change_4s. | |
#define | Wdt_change_8s() |
wdt_change_8s. | |
#define | Wdt_change_interrupt_16ms() |
wdt_change_interrupt_16ms. | |
#define | Wdt_change_interrupt_32ms() |
wdt_change_interrupt_32ms. | |
#define | Wdt_change_interrupt_64ms() |
wdt_change_interrupt_64ms. | |
#define | Wdt_change_interrupt_125ms() |
wdt_change_interrupt_125ms. | |
#define | Wdt_change_interrupt_250ms() |
wdt_change_interrupt_250ms. | |
#define | Wdt_change_interrupt_500ms() |
wdt_change_interrupt_500ms. | |
#define | Wdt_change_interrupt_1s() |
wdt_change_interrupt_1s. | |
#define | Wdt_change_interrupt_2s() |
wdt_change_interrupt_2s. | |
#define | Wdt_change_interrupt_4s() |
wdt_change_interrupt_4s. | |
#define | Wdt_change_interrupt_8s() |
wdt_change_interrupt_8s. | |
#define | Wdt_change_reserved5() |
#define | Soft_reset() {asm("jmp 0000");} |
Copyright (c) 2004 Atmel.
Use of this program is subject to Atmel's End User License Agreement. Please read file license.txt for copyright notice.
Definition in file wdt_drv.h.