mcu.h

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00001 /*H**************************************************************************
00002 * NAME:         mcu.h
00003 *----------------------------------------------------------------------------
00004 * Copyright (c) 2004 Atmel.
00005 *----------------------------------------------------------------------------
00006 * RELEASE:      at90usb128-demo-hidgen-1_0_0
00007 * REVISION:     1.6.6.9.2.19
00008 *----------------------------------------------------------------------------
00009 * PURPOSE:
00010 * SFR Description file for AtmegaUSB.
00011 *****************************************************************************/
00012 #ifndef MCU_H
00013 #define MCU_H
00014 
00015 /*==========================*/
00016 /* Predefined SFR Addresses */
00017 /*==========================*/
00018 
00019 /******************************************************************************/
00020 #if defined(__ICCAVR__) || defined(__IAR_SYSTEMS_ASM__)
00021 /******************************************************************************/
00022 SFR_B(PINA,   0x00) /* Input Pins, Port A */
00023 SFR_B(DDRA,   0x01) /* Data Direction Register, Port A */
00024 SFR_B(PORTA,  0x02) /* Data Register, Port A */
00025 
00026 SFR_B(PINB,   0x03) /* Input Pins, Port B */
00027 SFR_B(DDRB,   0x04) /* Data Direction Register, Port B */
00028 SFR_B(PORTB,  0x05) /* Data Register, Port B */
00029 
00030 SFR_B(PINC,   0x06) /* Input Pins, Port C */
00031 SFR_B(DDRC,   0x07) /* Data Direction Register, Port C */
00032 SFR_B(PORTC,  0x08) /* Data Register, Port C */
00033 
00034 SFR_B(PIND,   0x09) /* Input Pins, Port D */
00035 SFR_B(DDRD,   0x0A) /* Data Direction Register, Port D */
00036 SFR_B(PORTD,  0x0B) /* Data Register, Port D */
00037 
00038 SFR_B(PINE,   0x0C) /* Input Pins, Port E */
00039 SFR_B(DDRE,   0x0D) /* Data Direction Register, Port E */
00040 SFR_B(PORTE,  0x0E) /* Data Register, Port E */
00041 
00042 SFR_B(PINF,   0x0F) /* Input Pins, Port F */
00043 SFR_B(DDRF,   0x10) /* Data Direction Register, Port F */
00044 SFR_B(PORTF,  0x11) /* Data Register, Port F */
00045 
00046 SFR_B(PING,   0x12) /* Input Pins, Port G */
00047 SFR_B(DDRG,   0x13) /* Data Direction Register, Port G */
00048 SFR_B(PORTG,  0x14) /* Data Register, Port G */
00049 
00050 SFR_B(TIFR0,   0x15) /* Timer/Counter Interrupt Flag register 0*/
00051 SFR_B(TIFR1,   0x16) /* Timer/Counter Interrupt Flag register 1*/
00052 SFR_B(TIFR2,   0x17) /* Timer/Counter Interrupt Flag register 2*/
00053 SFR_B(TIFR3,   0x18) /* Timer/Counter Interrupt Flag register 3*/
00054 
00055 SFR_B(EIFR,   0x1C)     /* External Interrupt Flag Register */
00056 SFR_B(EIMSK,  0x1D)     /* External Interrupt Mask Register */
00057 
00058 SFR_B(GPIOR0,  0x1E)     /* General Purpose Register 0 */
00059 
00060 SFR_B(EECR,   0x1F)     /* EEPROM Control Register */
00061 SFR_B(EEDR,   0x20)     /* EEPROM Data Register */
00062 SFR_W(EEAR,   0x21)     /* EEPROM Address Register */
00063 
00064 SFR_B(GTCCR,  0x23)     /* General Purpose Register */
00065 
00066 SFR_B(TCCR0A,  0x24)     /* Timer/Counter 0 Control Register */
00067 SFR_B(TCNT0,   0x26)     /* Timer/Counter 0 */
00068 SFR_B(OCR0A,   0x27)     /* Timer/Counter 0 Output Compare Register */
00069 
00070 SFR_B(GPIOR1,  0x2A)     /* General Purpose Register 1 */
00071 SFR_B(GPIOR2,  0x2B)     /* General Purpose Register 2 */
00072 
00073 SFR_B(SPCR,   0x2C)     /* SPI Control Register */
00074 SFR_B(SPSR,   0x2D)     /* SPI Status Register */
00075 SFR_B(SPDR,   0x2E)     /* SPI I/O Data Register */
00076 
00077 SFR_B(ACSR,   0x30)     /* Analog Comparator Control and Status Register */
00078 
00079 SFR_B(OCDR,   0x31)     /* On-Chip Debug Register */
00080 
00081 SFR_B(SMCR,   0x33)    /* Sleep Mode Control Register */
00082 SFR_B(MCUSR,  0x34)    /* MCU Status Register */
00083 SFR_B(MCUCR,  0x35)    /* MCU Control Register */
00084 
00085 SFR_B(SPMCSR, 0x37)     /* Store Program Memory Control and Status Register */
00086 
00087 SFR_B(RAMPZ,  0x3B)     /* RAM Page Z Select Register */
00088 
00089 SFR_W(SP,     0x3D)     /* Stack Pointer */
00090 SFR_B(SREG,   0x3F)     /* Status Register */
00091 
00092 SFR_B(PLLCSR,    0x29); /* PLL Control and Status Register*/
00093 
00094 SFR_B_EXT(WDTCR,  0x60)     /* Watchdog Timer Control Register for compatibility*/
00095 SFR_B_EXT(WDTCSR,  0x60)    /* Watchdog Timer Control Register */
00096 SFR_B_EXT(CLKPR,  0x61)     /* Clock Prescale Register */
00097 SFR_B_EXT(OSCCAL, 0x66)     /* Oscillator Calibration Register */
00098 
00099 SFR_B_EXT(EICRA,  0x69)     /* External Interrupt Control Register A */
00100 SFR_B_EXT(EICRB,  0x6A)     /* External Interrupt Control Register B */
00101 
00102 SFR_B_EXT(TIMSK0,  0x6E)     /* Timer/Counter 0 Interrupt Mask Register */
00103 SFR_B_EXT(TIMSK1,  0x6F)     /* Timer/Counter 1 Interrupt Mask Register */
00104 SFR_B_EXT(TIMSK2,  0x70)     /* Timer/Counter 2 Interrupt Mask Register */
00105 SFR_B_EXT(TIMSK3,  0x71)     /* Timer/Counter 3 Interrupt Mask Register */
00106 
00107 SFR_B_EXT(XMCRA,  0x74)     /* External Memory Control Register A */
00108 SFR_B_EXT(XMCRB,  0x75)     /* External Memory Control Register B */
00109 
00110 SFR_W_EXT(ADC,    0x78)     /* ADC Data register */
00111 SFR_B_EXT(ADCSRA, 0x7A)     /* ADC Control and Status Register A */
00112 SFR_B_EXT(ADCSRB, 0x7B)     /* ADC Control and Status Register B */
00113 SFR_B_EXT(ADMUX,  0x7C)     /* ADC Multiplexer Selection Register */
00114 
00115 SFR_B_EXT(DIDR0,  0x7E)     /* Digital Input Disable Register 0 */
00116 SFR_B_EXT(DIDR1,  0x7F)     /* Digital Input Disable Register 1 */
00117 
00118 SFR_B_EXT(TCCR1A, 0x80)     /* Timer/Counter 1 Control Register A */
00119 SFR_B_EXT(TCCR1B, 0x81)     /* Timer/Counter 1 Control Register B */
00120 SFR_B_EXT(TCCR1C, 0x82)     /* Timer/Counter 1 Control Register C */
00121 SFR_W_EXT(TCNT1,  0x84)     /* Timer/Counter 1 Register */
00122 SFR_W_EXT(ICR1,   0x86)     /* Timer/Counter 1 Input Capture Register */
00123 SFR_W_EXT(OCR1A,  0x88)     /* Timer/Counter 1 Output Compare Register A */
00124 SFR_W_EXT(OCR1B,  0x8A)     /* Timer/Counter 1 Output Compare Register B */
00125 SFR_W_EXT(OCR1C,  0x8C)     /* Timer/Counter 1 Output Compare Register C */
00126 
00127 SFR_B_EXT(TCCR3A, 0x90)     /* Timer/Counter 3 Control Register A */
00128 SFR_B_EXT(TCCR3B, 0x91)     /* Timer/Counter 3 Control Register B */
00129 SFR_B_EXT(TCCR3C, 0x92)     /* Timer/Counter 3 Control Register C */
00130 SFR_W_EXT(TCNT3,  0x94)     /* Timer/Counter 3 Register */
00131 SFR_W_EXT(ICR3,   0x96)     /* Timer/Counter 3 Input Capture Register */
00132 SFR_W_EXT(OCR3A,  0x98)     /* Timer/Counter 3 Output Compare Register A */
00133 SFR_W_EXT(OCR3B,  0x9A)     /* Timer/Counter 3 Output Compare Register B */
00134 SFR_W_EXT(OCR3C,  0x9C)     /* Timer/Counter 3 Output Compare Register C */
00135 
00136 SFR_B_EXT(TCCR2A, 0xB0)     /* Timer/Counter 2 Control Register A */
00137 SFR_B_EXT(TCCR2B, 0xB1)     /* Timer/Counter 2 Control Register A */
00138 SFR_B_EXT(TCNT2,  0xB2)     /* Timer/Counter 2 Register */
00139 SFR_B_EXT(OCR2A,  0xB3)     /* Timer/Counter 2 Output Compare Register A */
00140 
00141 SFR_B_EXT(ASSR,   0xB6)     /* Asynchronous mode Status Register */
00142 
00143 SFR_B_EXT(TWBR,   0xB8)     /* TWI Bit Rate Register */
00144 SFR_B_EXT(TWSR,   0XB9)     /* TWI Status Register */
00145 SFR_B_EXT(TWAR,   0xBA)     /* TWI Address Register */
00146 SFR_B_EXT(TWDR,   0xBB)     /* TWI Data Register */
00147 SFR_B_EXT(TWCR,   0xBC)     /* TWI Control Register */
00148 
00149 
00150 SFR_B_EXT(UCSR1A, 0xC8)     /* USART1 Control and Status Register A */
00151 SFR_B_EXT(UCSR1B, 0xC9)     /* USART1 Control and Status Register B */
00152 SFR_B_EXT(UCSR1C, 0xCA)     /* USART1 Control and Status Register C */
00153 SFR_W_EXT(UBRR1,  0xCC)     /* USART1 Baud Rate Register Low */
00154 //SFR_B_EXT(UBRR1L, 0xCC)
00155 //SFR_B_EXT(UBRR1H, 0xCD)
00156 SFR_B_EXT(UDR1,   0xCE)     /* USART1 I/O Data Register */
00157 
00158 SFR_B_EXT(PCICR, 0x68)      /* Pin Change interrupt enable */
00159 SFR_B_EXT(PCIFR, 0x3B)      /* Pin Change interrupt flag*/
00160 SFR_B_EXT(PCMSK0, 0x6B)     /* Pin Change interrupt mask */
00161 
00162 
00163 
00164 // USB CONTROLLER
00165 //USB Hardware configuration
00166 SFR_B_EXT(UHWCON,    0xD7);
00167 
00168 // USB General
00169 // Page 1
00170 SFR_B_EXT(USBCON,    0xD8);
00171 SFR_B_EXT(USBSTA,    0xD9);
00172 SFR_B_EXT(USBINT,    0xDA);
00173 SFR_B_EXT(UDPADDH,   0xDC);
00174 SFR_B_EXT(UDPADDL,   0xDB);
00175 SFR_B_EXT(OTGCON,    0xDD);
00176 SFR_B_EXT(OTGTCON,   0xF9);
00177 SFR_B_EXT(OTGIEN,    0xDE);
00178 SFR_B_EXT(OTGINT,    0xDF);
00179 
00180 // USB Device
00181 // Page 1
00182 SFR_B_EXT(UDCON,     0xE0);
00183 SFR_B_EXT(UDINT,     0xE1);
00184 SFR_B_EXT(UDIEN,     0xE2);
00185 SFR_B_EXT(UDADDR,    0xE3);
00186 SFR_B_EXT(UDFNUMH,   0xE5);
00187 SFR_B_EXT(UDFNUML,   0xE4);
00188 SFR_B_EXT(UDMFN,     0xE6);
00189 SFR_B_EXT(UDTST,     0xE7);
00190 
00191 // USB Endpoint
00192 // Page 1
00193 SFR_B_EXT(UENUM,     0xE9);
00194 SFR_B_EXT(UERST,     0xEA);
00195 SFR_B_EXT(UECONX,    0xEB);
00196 SFR_B_EXT(UECFG0X,   0xEC);
00197 SFR_B_EXT(UECFG1X,   0xED);
00198 SFR_B_EXT(UESTA0X,   0xEE);
00199 SFR_B_EXT(UESTA1X,   0xEF);
00200 SFR_B_EXT(UEINTX,    0xE8);
00201 SFR_B_EXT(UEIENX,    0xF0);
00202 SFR_B_EXT(UEDATX,    0xF1);
00203 SFR_B_EXT(UEBCHX,    0xF3);
00204 SFR_B_EXT(UEBCLX,    0xF2);
00205 SFR_B_EXT(UEINT,     0xF4);
00206 
00207 // USB Host
00208 // Page 1
00209 SFR_B_EXT(UHCON,     0x9E);
00210 SFR_B_EXT(UHINT,     0x9F);
00211 SFR_B_EXT(UHIEN,     0xA0);
00212 SFR_B_EXT(UHADDR,    0xA1);
00213 SFR_B_EXT(UHFNUMH,   0xA3);
00214 SFR_B_EXT(UHFNUML,   0xA2);
00215 SFR_B_EXT(UHFLEN,    0xA4);
00216 
00217 // USB Pipe
00218 // Page 1
00219 SFR_B_EXT(UPNUM,     0xA7);
00220 SFR_B_EXT(UPRST,     0xA8);
00221 SFR_B_EXT(UPCONX,    0xA9);
00222 SFR_B_EXT(UPCFG0X,   0xAA);
00223 SFR_B_EXT(UPCFG1X,   0xAB);
00224 SFR_B_EXT(UPCFG2X,   0xAD);
00225 SFR_B_EXT(UPSTAX,    0xAC);
00226 SFR_B_EXT(UPINRQX,   0xA5);
00227 SFR_B_EXT(UPERRX,    0xF5);
00228 SFR_B_EXT(UPINTX,    0xA6);
00229 SFR_B_EXT(UPIENX,    0xAE);
00230 SFR_B_EXT(UPDATX,    0xAF);
00231 SFR_B_EXT(UPBCHX,    0xF7);
00232 SFR_B_EXT(UPBCLX,    0xF6);
00233 SFR_B_EXT(UPINT,     0xF8);
00234 
00235 
00236 
00237 /*==============================*/
00238 /* Interrupt Vector Definitions */
00239 /*==============================*/
00240 /* NB! vectors are specified as byte addresses */
00241 #define    RESET_vect                  (0x00)
00242 #define    INT0_vect                   (0x04)
00243 #define    INT1_vect                   (0x08)
00244 #define    INT2_vect                   (0x0C)
00245 #define    INT3_vect                   (0x10)
00246 #define    INT4_vect                   (0x14)
00247 #define    INT5_vect                   (0x18)
00248 #define    INT6_vect                   (0x1C)
00249 #define    INT7_vect                   (0x20)
00250 #define    PCINT0_vect                 (0x24)
00251 #define    USB_GENERAL_vect            (0x28)
00252 #define    USB_ENDPOINT_PIPE_vect      (0x2C)
00253 #define    WDT_vect                    (0x30)
00254 #define    TIMER2_COMPA_vect           (0x34)
00255 #define    TIMER2_COMPB_vect           (0x38)
00256 #define    TIMER2_OVF_vect             (0x3C)
00257 #define    TIMER1_CAPT_vect            (0x40)
00258 #define    TIMER1_COMPA_vect           (0x44)
00259 #define    TIMER1_COMPB_vect           (0x48)
00260 #define    TIMER1_COMPC_vect           (0x4C)
00261 #define    TIMER1_OVF_vect             (0x50)
00262 #define    TIMER0_COMPA_vect           (0x54)
00263 #define    TIMER0_COMPB_vect           (0x58)
00264 #define    TIMER0_OVF_vect             (0x5C)
00265 #define    SPI_STC_vect                (0x60)
00266 #define    USART1_RXC_vect             (0x64)
00267 #define    USART1_UDRE_vect            (0x68)
00268 #define    USART1_TXC_vect             (0x6C)
00269 #define    ANA_COMP_vect               (0x70)
00270 #define    ADC_vect                    (0x74)
00271 #define    EE_RDY_vect                 (0x78)
00272 #define    TIMER3_CAPT_vect            (0x7C)
00273 #define    TIMER3_COMPA_vect           (0x80)
00274 #define    TIMER3_COMPB_vect           (0x84)
00275 #define    TIMER3_COMPC_vect           (0x88)
00276 #define    TIMER3_OVF_vect             (0x8C)
00277 #define    TWI_vect                    (0x90)
00278 #define    SPM_RDY_vect                (0x94)
00279 
00280 #endif /* _IAR_ */
00281 /******************************************************************************/
00282 #ifdef __CODEVISIONAVR__
00283 /******************************************************************************/
00284 #define PINA    (*(volatile unsigned char *)0x20)  /* Input Pins, Port A */
00285 #define DDRA    (*(volatile unsigned char *)0x21) /* Data Direction Register, Port A */
00286 #define PORTA   (*(volatile unsigned char *)0x22) /* Data Register, Port A */
00287 
00288 #define PINB    (*(volatile unsigned char *)0x23) /* Input Pins, Port B */
00289 #define DDRB    (*(volatile unsigned char *)0x24) /* Data Direction Register, Port B */
00290 #define PORTB   (*(volatile unsigned char *)0x25) /* Data Register, Port B */
00291 
00292 #define PINC    (*(volatile unsigned char *)0x26) /* Input Pins, Port C */
00293 #define DDRC    (*(volatile unsigned char *)0x27) /* Data Direction Register, Port C */
00294 #define PORTC   (*(volatile unsigned char *)0x28) /* Data Register, Port C */
00295 
00296 #define PIND    (*(volatile unsigned char *)0x29) /* Input Pins, Port D */
00297 #define DDRD    (*(volatile unsigned char *)0x2A) /* Data Direction Register, Port D */
00298 #define PORTD   (*(volatile unsigned char *)0x2B) /* Data Register, Port D */
00299 
00300 #define PINE    (*(volatile unsigned char *)0x2C) /* Input Pins, Port E */
00301 #define DDRE    (*(volatile unsigned char *)0x2D) /* Data Direction Register, Port E */
00302 #define PORTE   (*(volatile unsigned char *)0x2E) /* Data Register, Port E */
00303 
00304 #define PINF    (*(volatile unsigned char *)0x2F) /* Input Pins, Port F */
00305 #define DDRF    (*(volatile unsigned char *)0x30) /* Data Direction Register, Port F */
00306 #define PORTF   (*(volatile unsigned char *)0x31) /* Data Register, Port F */
00307 
00308 #define PING    (*(volatile unsigned char *)0x32) /* Input Pins, Port G */
00309 #define DDRG    (*(volatile unsigned char *)0x33) /* Data Direction Register, Port G */
00310 #define PORTG   (*(volatile unsigned char *)0x34) /* Data Register, Port G */
00311 
00312 #define TIFR0   (*(volatile unsigned char *)0x35) /* Timer/Counter Interrupt Flag register 0*/
00313 #define TIFR1   (*(volatile unsigned char *)0x36) /* Timer/Counter Interrupt Flag register 1*/
00314 #define TIFR2   (*(volatile unsigned char *)0x37) /* Timer/Counter Interrupt Flag register 2*/
00315 #define TIFR3   (*(volatile unsigned char *)0x38) /* Timer/Counter Interrupt Flag register 3*/
00316 
00317 #define EIFR    (*(volatile unsigned char *)0x3C)     /* External Interrupt Flag Register */
00318 #define EIMSK   (*(volatile unsigned char *)0x3D)     /* External Interrupt Mask Register */
00319 
00320 #define GPIOR0  (*(volatile unsigned char *)0x3E)     /* General Purpose Register 0 */
00321 
00322 #define EECR    (*(volatile unsigned char *)0x3F)     /* EEPROM Control Register */
00323 #define EEDR    (*(volatile unsigned char *)0x40)     /* EEPROM Data Register */
00324 #define EEAR    (*(volatile unsigned int *)0x41)     /* EEPROM Address Register */
00325 
00326 #define GTCCR   (*(volatile unsigned char *)0x43)     /* General Purpose Register */
00327 
00328 #define TCCR0A  (*(volatile unsigned char *)0x44)     /* Timer/Counter 0 Control Register */
00329 #define TCNT0   (*(volatile unsigned char *)0x46)     /* Timer/Counter 0 */
00330 #define OCR0A   (*(volatile unsigned char *)0x47)     /* Timer/Counter 0 Output Compare Register */
00331 
00332 #define GPIOR1  (*(volatile unsigned char *)0x4A)     /* General Purpose Register 1 */
00333 #define GPIOR2  (*(volatile unsigned char *)0x4B)     /* General Purpose Register 2 */
00334 
00335 #define SPCR    (*(volatile unsigned char *)0x4C)     /* SPI Control Register */
00336 #define SPSR    (*(volatile unsigned char *)0x4D)     /* SPI Status Register */
00337 #define SPDR    (*(volatile unsigned char *)0x4E)     /* SPI I/O Data Register */
00338 
00339 #define ACSR    (*(volatile unsigned char *)0x50)     /* Analog Comparator Control and Status Register */
00340 
00341 #define OCDR    (*(volatile unsigned char *)0x51)     /* On-Chip Debug Register */
00342 
00343 #define SMCR    (*(volatile unsigned char *)0x53)    /* Sleep Mode Control Register */
00344 #define MCUSR   (*(volatile unsigned char *)0x53)    /* MCU Status Register */
00345 #define MCUCR   (*(volatile unsigned char *)0x53)    /* MCU Control Register */
00346 
00347 #define SPMCSR  (*(volatile unsigned char *)0x57)     /* Store Program Memory Control and Status Register */
00348 
00349 #define RAMPZ   (*(volatile unsigned char *)0x5B)     /* RAM Page Z Select Register */
00350 
00351 #define SP      (*(volatile unsigned int *)0x5D)     /* Stack Pointer */
00352 #define SREG    (*(volatile unsigned char *)0x5F)     /* Status Register */
00353 
00354 #define WDTCR   (*(volatile unsigned char *)0x60)     /* Watchdog Timer Control Register */
00355 #define CLKPR   (*(volatile unsigned char *)0x61)     /* Clock Prescale Register */
00356 #define OSCCAL  (*(volatile unsigned char *)0x66)     /* Oscillator Calibration Register */
00357 
00358 #define EICRA   (*(volatile unsigned char *)0x69)     /* External Interrupt Control Register A */
00359 #define EICRB   (*(volatile unsigned char *)0x6A)     /* External Interrupt Control Register B */
00360 
00361 #define TIMSK0  (*(volatile unsigned char *)0x6E)     /* Timer/Counter 0 Interrupt Mask Register */
00362 #define TIMSK1  (*(volatile unsigned char *)0x6F)     /* Timer/Counter 1 Interrupt Mask Register */
00363 #define TIMSK2  (*(volatile unsigned char *)0x70)     /* Timer/Counter 2 Interrupt Mask Register */
00364 #define TIMSK3  (*(volatile unsigned char *)0x71)     /* Timer/Counter 3 Interrupt Mask Register */
00365 
00366 #define XMCRA   (*(volatile unsigned char *)0x74)     /* External Memory Control Register A */
00367 #define XMCRB   (*(volatile unsigned char *)0x75)     /* External Memory Control Register B */
00368 
00369 #define ADC     (*(volatile unsigned int *)0x78)     /* ADC Data register */
00370 #define ADCSRA  (*(volatile unsigned char *)0x7A)     /* ADC Control and Status Register A */
00371 #define ADCSRB  (*(volatile unsigned char *)0x7B)     /* ADC Control and Status Register B */
00372 #define ADMUX   (*(volatile unsigned char *)0x7C)     /* ADC Multiplexer Selection Register */
00373 
00374 #define DIDR0   (*(volatile unsigned char *)0x7E)     /* Digital Input Disable Register 0 */
00375 #define DIDR1   (*(volatile unsigned char *)0x7F)     /* Digital Input Disable Register 1 */
00376 
00377 #define TCCR1A  (*(volatile unsigned char *)0x80)     /* Timer/Counter 1 Control Register A */
00378 #define TCCR1B  (*(volatile unsigned char *)0x81)     /* Timer/Counter 1 Control Register B */
00379 #define TCCR1C  (*(volatile unsigned char *)0x82)     /* Timer/Counter 1 Control Register C */
00380 #define TCNT1   (*(volatile unsigned int *)0x84)     /* Timer/Counter 1 Register */
00381 #define ICR1    (*(volatile unsigned int *)0x86)     /* Timer/Counter 1 Input Capture Register */
00382 #define OCR1A   (*(volatile unsigned int *)0x88)     /* Timer/Counter 1 Output Compare Register A */
00383 #define OCR1B   (*(volatile unsigned int *)0x8A)     /* Timer/Counter 1 Output Compare Register B */
00384 #define OCR1C   (*(volatile unsigned int *)0x8C)     /* Timer/Counter 1 Output Compare Register C */
00385 
00386 #define TCCR3A  (*(volatile unsigned char *)0x90)     /* Timer/Counter 3 Control Register A */
00387 #define TCCR3B  (*(volatile unsigned char *)0x91)     /* Timer/Counter 3 Control Register B */
00388 #define TCCR3C  (*(volatile unsigned char *)0x92)     /* Timer/Counter 3 Control Register C */
00389 #define TCNT3   (*(volatile unsigned int *)0x94)     /* Timer/Counter 3 Register */
00390 #define ICR3    (*(volatile unsigned int *)0x96)     /* Timer/Counter 3 Input Capture Register */
00391 #define OCR3A   (*(volatile unsigned int *)0x98)     /* Timer/Counter 3 Output Compare Register A */
00392 #define OCR3B   (*(volatile unsigned int *)0x9A)     /* Timer/Counter 3 Output Compare Register B */
00393 #define OCR3C   (*(volatile unsigned int *)0x9C)     /* Timer/Counter 3 Output Compare Register C */
00394 
00395 #define TCCR2A  (*(volatile unsigned char *)0xB0)     /* Timer/Counter 2 Control Register A */
00396 #define TCNT2   (*(volatile unsigned char *)0xB2)     /* Timer/Counter 2 Register */
00397 #define OCR2A   (*(volatile unsigned char *)0xB3)     /* Timer/Counter 2 Output Compare Register A */
00398 
00399 #define ASSR   (*(volatile unsigned char *)0xB6)     /* Asynchronous mode Status Register */
00400 
00401 #define TWBR   (*(volatile unsigned char *)0xB8)     /* TWI Bit Rate Register */
00402 #define TWSR   (*(volatile unsigned char *)0XB9)     /* TWI Status Register */
00403 #define TWAR   (*(volatile unsigned char *)0xBA)     /* TWI Address Register */
00404 #define TWDR   (*(volatile unsigned char *)0xBB)     /* TWI Data Register */
00405 #define TWCR   (*(volatile unsigned char *)0xBC)     /* TWI Control Register */
00406 
00407 #define UCSR0A  (*(volatile unsigned char *)0xC0)     /* USART0 Control and Status Register A */
00408 #define UCSR0B  (*(volatile unsigned char *)0xC1)     /* USART0 Control and Status Register B */
00409 #define UCSR0C  (*(volatile unsigned char *)0xC2)     /* USART0 Control and Status Register C */
00410 #define UBRR0   (*(volatile unsigned int *)0xC4)     /* USART0 Baud Rate Register  */
00411 #define UBRR0L  (*(volatile unsigned char *)0xC4)     /* USART0 Baud Rate Register Low */
00412 #define UBRR0H  (*(volatile unsigned char *)0xC5)     /* USART0 Baud Rate Register High */
00413 #define UDR0    (*(volatile unsigned char *)0xC6)     /* USART0 I/O Data Register */
00414 
00415 #define UCSR1A  (*(volatile unsigned char *)0xC8)     /* USART1 Control and Status Register A */
00416 #define UCSR1B  (*(volatile unsigned char *)0xC9)     /* USART1 Control and Status Register B */
00417 #define UCSR1C  (*(volatile unsigned char *)0xCA)     /* USART1 Control and Status Register C */
00418 #define UBRR1   (*(volatile unsigned int *)0xCC)     /* USART1 Baud Rate Register  */
00419 #define UBRR1L  (*(volatile unsigned char *)0xCC)     /* USART1 Baud Rate Register Low */
00420 #define UBRR1H  (*(volatile unsigned char *)0xCD)     /* USART1 Baud Rate Register High */
00421 #define UDR1    (*(volatile unsigned char *)0xCE)     /* USART1 I/O Data Register */
00422 
00423 
00424 
00425 /*==============================*/
00426 /* Interrupt Vector Definitions */
00427 /*==============================*/
00428 /* NB! vectors are specified as byte addresses */
00429 #define    RESET_vect           1
00430 #define    INT0_vect            2
00431 #define    INT1_vect            3
00432 #define    INT2_vect            4
00433 #define    INT3_vect            5
00434 #define    INT4_vect            6
00435 #define    INT5_vect            7
00436 #define    INT6_vect            8
00437 #define    INT7_vect            9
00438 #define    TIMER2_COMP_vect     10
00439 #define    TIMER2_OVF_vect      11
00440 #define    TIMER1_CAPT_vect     12
00441 #define    TIMER1_COMPA_vect    13
00442 #define    TIMER1_COMPB_vect    14
00443 #define    TIMER1_COMPC_vect    15
00444 #define    TIMER1_OVF_vect      16
00445 #define    TIMER0_COMP_vect     17
00446 #define    TIMER0_OVF_vect      18
00447 #define    CANIT_vect      19                
00448 #define    CANTOVF_vect    20       
00449 #define    SPI_STC_vect         21
00450 #define    USART0_RXC_vect      22
00451 #define    USART0_UDRE_vect     23
00452 #define    USART0_TXC_vect      24
00453 #define    ANA_COMP_vect        25
00454 #define    ADC_vect             26
00455 #define    EE_RDY_vect          27
00456 #define    TIMER3_CAPT_vect     28
00457 #define    TIMER3_COMPA_vect    29
00458 #define    TIMER3_COMPB_vect    30
00459 #define    TIMER3_COMPC_vect    31
00460 #define    TIMER3_OVF_vect      32
00461 #define    USART1_RXC_vect      33
00462 #define    USART1_UDRE_vect     34
00463 #define    USART1_TXC_vect      35
00464 #define    TWI_vect             36
00465 #define    SPM_RDY_vect         37
00466 
00467 #endif /* _ICC_*/
00468 
00469 
00470 
00471 /*==========================*/
00472 /* Bit Position Definitions */
00473 /*==========================*/
00474 /* PINA : Input Pins, Port A */
00475 #define    PINA7    7
00476 #define    PINA6    6
00477 #define    PINA5    5
00478 #define    PINA4    4
00479 #define    PINA3    3
00480 #define    PINA2    2
00481 #define    PINA1    1
00482 #define    PINA0    0
00483 
00484 /* DDRA : Data Direction Register, Port A */
00485 #define    DDA7     7
00486 #define    DDA6     6
00487 #define    DDA5     5
00488 #define    DDA4     4
00489 #define    DDA3     3
00490 #define    DDA2     2
00491 #define    DDA1     1
00492 #define    DDA0     0
00493 
00494 /* PORTA : Data Register, Port A */
00495 #define    PORTA7   7
00496 #define    PORTA6   6
00497 #define    PORTA5   5
00498 #define    PORTA4   4
00499 #define    PORTA3   3
00500 #define    PORTA2   2
00501 #define    PORTA1   1
00502 #define    PORTA0   0
00503 
00504 /* PORTA : Data Register, Port A */
00505 #define    PA7      7
00506 #define    PA6      6
00507 #define    PA5      5
00508 #define    PA4      4
00509 #define    PA3      3
00510 #define    PA2      2
00511 #define    PA1      1
00512 #define    PA0      0
00513 
00514 /* PINB : Input Pins, Port B */
00515 #define    PINB7    7
00516 #define    PINB6    6
00517 #define    PINB5    5
00518 #define    PINB4    4
00519 #define    PINB3    3
00520 #define    PINB2    2
00521 #define    PINB1    1
00522 #define    PINB0    0
00523 
00524 /* DDRB : Data Direction Register, Port B */
00525 #define    DDB7     7
00526 #define    DDB6     6
00527 #define    DDB5     5
00528 #define    DDB4     4
00529 #define    DDB3     3
00530 #define    DDB2     2
00531 #define    DDB1     1
00532 #define    DDB0     0
00533 
00534 /* PORTB : Data Register, Port B */
00535 #define    PB7      7
00536 #define    PB6      6
00537 #define    PB5      5
00538 #define    PB4      4
00539 #define    PB3      3
00540 #define    PB2      2
00541 #define    PB1      1
00542 #define    PB0      0
00543 
00544 /* PORTB : Data Register, Port B */
00545 #define    PORTB7   7
00546 #define    PORTB6   6
00547 #define    PORTB5   5
00548 #define    PORTB4   4
00549 #define    PORTB3   3
00550 #define    PORTB2   2
00551 #define    PORTB1   1
00552 #define    PORTB0   0
00553 
00554 /* PINC : Input Pins, Port C */
00555 #define    PINC7    7
00556 #define    PINC6    6
00557 #define    PINC5    5
00558 #define    PINC4    4
00559 #define    PINC3    3
00560 #define    PINC2    2
00561 #define    PINC1    1
00562 #define    PINC0    0
00563 
00564 /* DDRC : Data Direction Register, Port C */
00565 #define    DDC7     7
00566 #define    DDC6     6
00567 #define    DDC5     5
00568 #define    DDC4     4
00569 #define    DDC3     3
00570 #define    DDC2     2
00571 #define    DDC1     1
00572 #define    DDC0     0
00573 
00574 /* PORTC : Data Register, Port C */
00575 #define    PC7      7
00576 #define    PC6      6
00577 #define    PC5      5
00578 #define    PC4      4
00579 #define    PC3      3
00580 #define    PC2      2
00581 #define    PC1      1
00582 #define    PC0      0
00583 
00584 /* PORTC : Data Register, Port C */
00585 #define    PORTC7   7
00586 #define    PORTC6   6
00587 #define    PORTC5   5
00588 #define    PORTC4   4
00589 #define    PORTC3   3
00590 #define    PORTC2   2
00591 #define    PORTC1   1
00592 #define    PORTC0   0
00593 
00594 /* PIND : Input Pins, Port D */
00595 #define    PIND7    7
00596 #define    PIND6    6
00597 #define    PIND5    5
00598 #define    PIND4    4
00599 #define    PIND3    3
00600 #define    PIND2    2
00601 #define    PIND1    1
00602 #define    PIND0    0
00603 
00604 /* DDRD : Data Direction Register, Port D */
00605 #define    DDD7     7
00606 #define    DDD6     6
00607 #define    DDD5     5
00608 #define    DDD4     4
00609 #define    DDD3     3
00610 #define    DDD2     2
00611 #define    DDD1     1
00612 #define    DDD0     0
00613 
00614 /* PORTD : Data Register, Port D */
00615 #define    PD7      7
00616 #define    PD6      6
00617 #define    PD5      5
00618 #define    PD4      4
00619 #define    PD3      3
00620 #define    PD2      2
00621 #define    PD1      1
00622 #define    PD0      0
00623 
00624 /* PORTD : Data Register, Port D */
00625 #define    PORTD7   7
00626 #define    PORTD6   6
00627 #define    PORTD5   5
00628 #define    PORTD4   4
00629 #define    PORTD3   3
00630 #define    PORTD2   2
00631 #define    PORTD1   1
00632 #define    PORTD0   0
00633 
00634 /* PINE : Input Pins, Port E */
00635 #define    PINE7    7
00636 #define    PINE6    6
00637 #define    PINE5    5
00638 #define    PINE4    4
00639 #define    PINE3    3
00640 #define    PINE2    2
00641 #define    PINE1    1
00642 #define    PINE0    0
00643 
00644 /* DDRE : Data Direction Register, Port E */
00645 #define    DDE7     7
00646 #define    DDE6     6
00647 #define    DDE5     5
00648 #define    DDE4     4
00649 #define    DDE3     3
00650 #define    DDE2     2
00651 #define    DDE1     1
00652 #define    DDE0     0
00653 
00654 /* PORTE : Data Register, Port E */
00655 #define    PE7      7
00656 #define    PE6      6
00657 #define    PE5      5
00658 #define    PE4      4
00659 #define    PE3      3
00660 #define    PE2      2
00661 #define    PE1      1
00662 #define    PE0      0
00663 
00664 /* PORTE : Data Register, Port E */
00665 #define    PORTE7   7
00666 #define    PORTE6   6
00667 #define    PORTE5   5
00668 #define    PORTE4   4
00669 #define    PORTE3   3
00670 #define    PORTE2   2
00671 #define    PORTE1   1
00672 #define    PORTE0   0
00673 
00674 /* PINF : Input Pins, Port F */
00675 #define    PINF7    7
00676 #define    PINF6    6
00677 #define    PINF5    5
00678 #define    PINF4    4
00679 #define    PINF3    3
00680 #define    PINF2    2
00681 #define    PINF1    1
00682 #define    PINF0    0
00683 
00684 /* DDRF : Data Direction Register, Port F */
00685 #define    DDF7     7
00686 #define    DDF6     6
00687 #define    DDF5     5
00688 #define    DDF4     4
00689 #define    DDF3     3
00690 #define    DDF2     2
00691 #define    DDF1     1
00692 #define    DDF0     0
00693 
00694 /* PORTF : Data Register, Port F */
00695 #define    PF7      7
00696 #define    PF6      6
00697 #define    PF5      5
00698 #define    PF4      4
00699 #define    PF3      3
00700 #define    PF2      2
00701 #define    PF1      1
00702 #define    PF0      0
00703 
00704 /* PORTF : Data Register, Port F */
00705 #define    PORTF7   7
00706 #define    PORTF6   6
00707 #define    PORTF5   5
00708 #define    PORTF4   4
00709 #define    PORTF3   3
00710 #define    PORTF2   2
00711 #define    PORTF1   1
00712 #define    PORTF0   0
00713 
00714 /* Input Pins, Port G */
00715 #define    PING4    4
00716 #define    PING3    3
00717 #define    PING2    2
00718 #define    PING1    1
00719 #define    PING0    0
00720 
00721 /* DDRG : Data Direction Register, Port G */
00722 #define    DDG4     4
00723 #define    DDG3     3
00724 #define    DDG2     2
00725 #define    DDG1     1
00726 #define    DDG0     0
00727 
00728 /* PORTG : Data Register, Port G */
00729 #define    PG4      4
00730 #define    PG3      3
00731 #define    PG2      2
00732 #define    PG1      1
00733 #define    PG0      0
00734 
00735 /* PORTG : Data Register, Port G */
00736 #define    PORTG4   4
00737 #define    PORTG3   3
00738 #define    PORTG2   2
00739 #define    PORTG1   1
00740 #define    PORTG0   0
00741 
00742 /* TFR0 : Timer/Counter Interrupt Flag Register 0 */
00743 #define    OCF0A    1
00744 #define    TOV0     0
00745 
00746 /* TFR1 : Timer/Counter Interrupt Flag Register 1 */
00747 #define    ICF1     5
00748 #define    OCF1C    3
00749 #define    OCF1B    2
00750 #define    OCF1A    1
00751 #define    TOV1     0
00752 
00753 /* TFR2 : Timer/Counter Interrupt Flag Register 2 */
00754 #define    OCF2A    1
00755 #define    TOV2     0
00756 
00757 /* TFR3 : Timer/Counter Interrupt Flag Register 3 */
00758 #define    ICF3     5
00759 #define    OCF3C    3
00760 #define    OCF3B    2
00761 #define    OCF3A    1
00762 #define    TOV3     0
00763 
00764 /* EIFR : External Interrupt Flag Register */
00765 #define    INTF7    7
00766 #define    INTF6    6
00767 #define    INTF5    5
00768 #define    INTF4    4
00769 #define    INTF3    3
00770 #define    INTF2    2
00771 #define    INTF1    1
00772 #define    INTF0    0
00773 
00774 /* EIMSK : External Interrupt Mask Register */
00775 #define    INT7     7
00776 #define    INT6     6
00777 #define    INT5     5
00778 #define    INT4     4
00779 #define    INT3     3
00780 #define    INT2     2
00781 #define    INT1     1
00782 #define    INT0     0
00783 
00784 /* EICRA : External Interrupt Control Register A*/
00785 #define    ISC31     7
00786 #define    ISC30     6
00787 #define    ISC21     5
00788 #define    ISC20     4
00789 #define    ISC11     3
00790 #define    ISC10     2
00791 #define    ISC01     1
00792 #define    ISC00     0
00793 
00794 /* EICRA : External Interrupt Control Register B*/
00795 #define    ISC71     7
00796 #define    ISC70     6
00797 #define    ISC61     5
00798 #define    ISC60     4
00799 #define    ISC51     3
00800 #define    ISC50     2
00801 #define    ISC41     1
00802 #define    ISC40     0
00803 
00804 /* EECR : EEPROM Control Register */
00805 #define    EERIE    3
00806 #define    EEMWE    2
00807 #define    EEWE     1
00808 #define    EERE     0
00809 
00810 /* GTCCR : General Timer Control Register */
00811 #define    TSM      7
00812 #define    PSR2     1
00813 #define    PSR310   0
00814 
00815 
00816 /* TCCR0A : Timer/Counter 0 Control Register */
00817 #define    FOC0A     7
00818 #define    WGM00    6
00819 #define    COM0A1    5
00820 #define    COM0A0    4
00821 #define    WGM01    3
00822 #define    CS02     2
00823 #define    CS01     1
00824 #define    CS00     0
00825 
00826 /* SPCR : SPI Control Register */
00827 #define    SPIE     7
00828 #define    SPE      6
00829 #define    DORD     5
00830 #define    MSTR     4
00831 #define    CPOL     3
00832 #define    CPHA     2
00833 #define    SPR1     1
00834 #define    SPR0     0
00835 
00836 /* SPSR : SPI Status Register */
00837 #define    SPIF     7
00838 #define    WCOL     6
00839 #define    SPI2X    0
00840 
00841 /* ACSR : Analog Comparator Control and Status Register */
00842 #define    ACD      7
00843 #define    ACBG     6
00844 #define    ACO      5
00845 #define    ACI      4
00846 #define    ACIE     3
00847 #define    ACIC     2
00848 #define    ACIS1    1
00849 #define    ACIS0    0
00850 
00851 /* OCDR : On-Chip Debug Register */
00852 #define    IDRD     7
00853 #define    OCDR7    7
00854 #define    OCDR6    6
00855 #define    OCDR5    5
00856 #define    OCDR4    4
00857 #define    OCDR3    3
00858 #define    OCDR2    2
00859 #define    OCDR1    1
00860 #define    OCDR0    0
00861 
00862 /* SMCR : Sleep Mode Control Register */
00863 #define    SM2      3
00864 #define    SM1      2
00865 #define    SM0      1
00866 #define    SE       0
00867 
00868 /* MCUSR : MCU general Status Register */
00869 #define    JTRF     4
00870 #define    WDRF     3
00871 #define    BORF     2
00872 #define    EXTRF    1
00873 #define    PORF     0
00874 
00875 /* MCUCR : MCU general Control Register */
00876 #define    JTD      7
00877 #define    PUD      4
00878 #define    IVSEL    1
00879 #define    IVCE     0
00880 
00881 /* SPMCR : Store Program Memory Control and Status Register */
00882 #define    SPMIE    7
00883 #define    RWWSB    6
00884 #define    SIGRD    5
00885 #define    RWWSRE   4
00886 #define    BLBSET   3
00887 #define    PGWRT    2
00888 #define    PGERS    1
00889 #define    SPMEN    0
00890 
00891 /* RAMPZ : RAM Page Z Select Register */
00892 #define    RAMPZ0   0
00893 
00894 /* SPH : Stack Pointer High */
00895 #define    SP15     7
00896 #define    SP14     6
00897 #define    SP13     5
00898 #define    SP12     4
00899 #define    SP11     3
00900 #define    SP10     2
00901 #define    SP9      1
00902 #define    SP8      0
00903 
00904 /* SPL : Stack Pointer Low */
00905 #define    SP7      7
00906 #define    SP6      6
00907 #define    SP5      5
00908 #define    SP4      4
00909 #define    SP3      3
00910 #define    SP2      2
00911 #define    SP1      1
00912 #define    SP0      0
00913 
00914 /* WTDCR : Watchdog Timer Control Register */
00915 #define    WDIF     7
00916 #define    WDIE     6
00917 #define    WDP3     5
00918 #define    WDCE     4
00919 #define    WDE      3
00920 #define    WDP2     2
00921 #define    WDP1     1
00922 #define    WDP0     0
00923 
00924 /* CLKPR : Source Clock Prescaler Register */
00925 #define    CKLPCE   7
00926 #define    CLKPCE   7 //for compatiblity
00927 #define    CKLPS3   3
00928 #define    CKLPS2   2
00929 #define    CKLPS1   1
00930 #define    CKLPS0   0
00931 
00932 /* TIMSK0 : Timer Interrupt Mask Register0 */
00933 #define    OCIE0A   1
00934 #define    TOIE0    0
00935 
00936 /* TIMSK1 : Timer Interrupt Mask Register1 */
00937 #define    ICIE1    5
00938 #define    OCIE1C   3
00939 #define    OCIE1B   2
00940 #define    OCIE1A   1
00941 #define    TOIE1    0
00942 
00943 /* TIMSK2 : Timer Interrupt Mask Register2 */
00944 #define    OCIE2A   1
00945 #define    TOIE2    0
00946 
00947 /* TIMSK3 : Timer Interrupt Mask Register3 */
00948 #define    ICIE3    5
00949 #define    OCIE3C   3
00950 #define    OCIE3B   2
00951 #define    OCIE3A   1
00952 #define    TOIE3    0
00953 
00954 /* XMCRA : External Memory Control A Register */
00955 #define    SRE      7
00956 #define    SRL2     6
00957 #define    SRL1     5
00958 #define    SRL0     4
00959 #define    SRW11    3
00960 #define    SRW10    2
00961 #define    SRW01    1
00962 #define    SRW00    0
00963 
00964 /* XMCRB : External Memory Control B Register */
00965 #define    XMBK     7
00966 #define    XMM2     2
00967 #define    XMM1     1
00968 #define    XMM0     0
00969 
00970 /* ADCSRA : ADC Control and Status Register A*/
00971 #define    ADEN     7
00972 #define    ADSC     6
00973 #define    ADATE    5
00974 #define    ADIF     4
00975 #define    ADIE     3
00976 #define    ADPS2    2
00977 #define    ADPS1    1
00978 #define    ADPS0    0
00979 
00980 /* ADCSRB : ADC Control and Status Register B*/
00981 #define    ADHSM   7
00982 #define    ACME     6
00983 #define    ADST2    2
00984 #define    ADST1    1
00985 #define    ADST0    0
00986 
00987 /* ADMUX : ADC Multiplexer Selection Register */
00988 #define    REFS1    7
00989 #define    REFS0    6
00990 #define    ADLAR    5
00991 #define    MUX4     4
00992 #define    MUX3     3
00993 #define    MUX2     2
00994 #define    MUX1     1
00995 #define    MUX0     0
00996 
00997 /* TCCR1A : Timer/Counter 1 Control Register A */
00998 #define    COM1A1   7
00999 #define    COM1A0   6
01000 #define    COM1B1   5
01001 #define    COM1B0   4
01002 #define    COM1C1   3
01003 #define    COM1C0   2
01004 #define    WGM11    1
01005 #define    WGM10    0
01006 
01007 /* TCCR1B : Timer/Counter 1 Control Register B */
01008 #define    ICNC1    7
01009 #define    ICES1    6
01010 #define    WGM13    4
01011 #define    WGM12    3
01012 #define    CS12     2
01013 #define    CS11     1
01014 #define    CS10     0
01015 
01016 /* TCCR1C : Timer/Counter 1 Control Register C */
01017 #define    FOC1A    7
01018 #define    FOC1B    6
01019 #define    FOC1C    5
01020 
01021 /* TCCR3A : Timer/Counter 3 Control Register A */
01022 #define    COM3A1   7
01023 #define    COM3A0   6
01024 #define    COM3B1   5
01025 #define    COM3B0   4
01026 #define    COM3C1   3
01027 #define    COM3C0   2
01028 #define    WGM31    1
01029 #define    WGM30    0
01030 
01031 /* TCCR3B : Timer/Counter 3 Control Register B */
01032 #define    ICNC3    7
01033 #define    ICES3    6
01034 #define    WGM33    4
01035 #define    WGM32    3
01036 #define    CS32     2
01037 #define    CS31     1
01038 #define    CS30     0
01039 
01040 /* TCCR3C : Timer/Counter 3 Control Register C */
01041 #define    FOC3A    7
01042 #define    FOC3B    6
01043 #define    FOC3C    5
01044 
01045 /* TCCR2A : Timer/Counter 2 Control Register A*/
01046 #define    FOC2     7
01047 #define    WGM20    6
01048 #define    COM21    5
01049 #define    COM20    4
01050 #define    WGM21    3
01051 #define    CS22     2
01052 #define    CS21     1
01053 #define    CS20     0
01054 
01055 /* ASSR : Asynchronous mode Status Register */
01056 #define    EXCLK    4
01057 #define    AS2      3
01058 #define    TCN2UB   2
01059 #define    OCR2UB   1
01060 #define    TCR2UB   0
01061 
01062 /* TWSR : TWI Status Register */
01063 #define    TWS7     7
01064 #define    TWS6     6
01065 #define    TWS5     5
01066 #define    TWS4     4
01067 #define    TWS3     3
01068 #define    TWPS1    1
01069 #define    TWPS0    0
01070 
01071 /* TWAR : TWI (slave) Address Register */
01072 #define    TWA6     7
01073 #define    TWA5     6
01074 #define    TWA4     5
01075 #define    TWA3     4
01076 #define    TWA2     3
01077 #define    TWA1     2
01078 #define    TWA0     1
01079 #define    TWGCE    0
01080 
01081 /* TWCR : TWI Control Register */
01082 #define    TWINT    7
01083 #define    TWEA     6
01084 #define    TWSTA    5
01085 #define    TWSTO    4
01086 #define    TWWC     3
01087 #define    TWEN     2
01088 #define    TWIE     0
01089 
01090 /* UCSR0A : USART0 Control and Status Register A */
01091 #define    RXC0     7
01092 #define    TXC0     6
01093 #define    UDRE0    5
01094 #define    FE0      4
01095 #define    DOR0     3
01096 #define    UPE0     2
01097 #define    U2X0     1
01098 #define    MPCM0    0
01099 
01100 /* UCSR0B : USART0 Control and Status Register B */
01101 #define    RXCIE0   7
01102 #define    TXCIE0   6
01103 #define    UDRIE0   5
01104 #define    RXEN0    4
01105 #define    TXEN0    3
01106 #define    UCSZ02   2
01107 #define    RXB80    1
01108 #define    TXB80    0
01109 
01110 /* UCSR0C : USART0 Control and Status Register C */
01111 #define    UMSEL0   6
01112 #define    UPM01    5
01113 #define    UPM00    4
01114 #define    USBS0    3
01115 #define    UCSZ01   2
01116 #define    UCSZ00   1
01117 #define    UCPOL0   0
01118 
01119 /* UCSR1A : USART1 Control and Status Register A */
01120 #define    RXC1     7
01121 #define    TXC1     6
01122 #define    UDRE1    5
01123 #define    FE1      4
01124 #define    DOR1     3
01125 #define    UPE1     2
01126 #define    U2X1     1
01127 #define    MPCM1    0
01128 
01129 /* UCSR1B : USART1 Control and Status Register B */
01130 #define    RXCIE1   7
01131 #define    TXCIE1   6
01132 #define    UDRIE1   5
01133 #define    RXEN1    4
01134 #define    TXEN1    3
01135 #define    UCSZ12   2
01136 #define    RXB81    1
01137 #define    TXB81    0
01138 
01139 /* UCSR1C : USART1 Control and Status Register C */
01140 #define    UMSEL1   6
01141 #define    UPM11    5
01142 #define    UPM10    4
01143 #define    USBS1    3
01144 #define    UCSZ11   2
01145 #define    UCSZ10   1
01146 #define    UCPOL1   0
01147 
01148 
01149 /* PCICR Pin Change Interrupt control */
01150 #define  PCIE0 0
01151 
01152 /* PCIFR Pin Change Interrupt flag */
01153 #define  PCIF0 0
01154 
01155 /* PCIMSK0 Pin Change Mask */
01156 #define  PCINT7    7
01157 #define  PCINT6    6
01158 #define  PCINT5    5
01159 #define  PCINT4    4
01160 #define  PCINT3    3
01161 #define  PCINT2    2
01162 #define  PCINT1    1
01163 #define  PCINT0    0
01164 
01165 
01166 /* ***** USB_DEVICE ******************* */
01167 /* UDCON -  */
01168 #define    DETACH          0       //
01169 #define    RMWKUP          1       //
01170 #define    LSM             2       //
01171 
01172 /* UDINT -  */
01173 #define    SUSPI           0       //
01174 #define    MSOFI           1       //
01175 #define    SOFI            2       //
01176 #define    EORSTI          3       //
01177 #define    WAKEUPI         4       //
01178 #define    EORSMI          5       //
01179 #define    UPRSMI          6       //
01180 
01181 /* UDIEN -  */
01182 #define    SUSPE           0       //
01183 #define    MSOFE           1       //
01184 #define    SOFE            2       //
01185 #define    EORSTE          3       //
01186 #define    WAKEUPE         4       //
01187 #define    EORSME          5       //
01188 #define    UPRSME          6       //
01189 
01190 /* UDADDR -  */
01191 #define    UDADDR0         0       //
01192 #define    UDADDR1         1       //
01193 #define    UDADDR2         2       //
01194 #define    UDADDR3         3       //
01195 #define    UDADDR4         4       //
01196 #define    UDADDR5         5       //
01197 #define    UDADDR6         6       //
01198 #define    ADDEN           7       //
01199 
01200 /* UDFNUML -  */
01201 #define    UDFNUML_0       0       //
01202 #define    UDFNUML_1       1       //
01203 #define    UDFNUML_2       2       //
01204 #define    UDFNUML_3       3       //
01205 #define    UDFNUML_4       4       //
01206 #define    UDFNUML_5       5       //
01207 #define    UDFNUML_6       6       //
01208 #define    UDFNUML_7       7       //
01209 
01210 /* UDFNUMH -  */
01211 #define    UDFNUMH_0       0       //
01212 #define    UDFNUMH_1       1       //
01213 #define    UDFNUMH_2       2       //
01214 
01215 /* UDMFN -  */
01216 #define    FNCERR          4       //
01217 
01218 /* UEINTX -  */
01219 #define    TXINI           0       //
01220 #define    STALLEDI        1       //
01221 #define    RXOUTI          2       //
01222 #define    RXSTPI          3       //
01223 #define    NAKOUTI         4       //
01224 #define    RWAL            5       //
01225 #define    NAKINI          6       //
01226 #define    FIFOCON         7       //
01227 
01228 /* UENUM -  */
01229 #define    UENUM_0         0       //
01230 #define    UENUM_1         1       //
01231 #define    UENUM_2         2       //
01232 
01233 /* UERST -  */
01234 #define    EPRST0          0       //
01235 #define    EPRST1          1       //
01236 #define    EPRST2          2       //
01237 #define    EPRST3          3       //
01238 #define    EPRST4          4       //
01239 #define    EPRST5          5       //
01240 #define    EPRST6          6       //
01241 
01242 /* UECONX -  */
01243 #define    EPEN            0       //
01244 #define    RSTDT           3       //
01245 #define    STALLRQC        4       //
01246 #define    STALLRQ         5       //
01247 
01248 /* UECFG0X -  */
01249 #define    EPDIR           0       //
01250 #define    NYETDIS         1       //
01251 #define    AUTOSW          2       //
01252 #define    ISOSW           3       //
01253 #define    EPTYPE0         6       //
01254 #define    EPTYPE1         7       //
01255 
01256 /* UECFG1X -  */
01257 #define    ALLOC           1       //
01258 #define    EPBK0           2       //
01259 #define    EPBK1           3       //
01260 #define    EPSIZE0         4       //
01261 #define    EPSIZE1         5       //
01262 #define    EPSIZE2         6       //
01263 
01264 /* UESTA0X -  */
01265 #define    NBUSYBK0        0       //
01266 #define    NBUSYBK1        1       //
01267 #define    DTSEQ0          2       //
01268 #define    DTSEQ1          3       //
01269 #define    ZLPSEEN         4       //
01270 #define    UNDERFI         5       //
01271 #define    OVERFI          6       //
01272 #define    CFGOK           7       //
01273 
01274 /* UESTA1X -  */
01275 #define    CURRBK0         0       //
01276 #define    CURRBK1         1       //
01277 #define    CTRLDIR         2       //
01278 
01279 /* UEIENX -  */
01280 #define    TXINE           0       //
01281 #define    STALLEDE        1       //
01282 #define    RXOUTE          2       //
01283 #define    RXSTPE          3       //
01284 #define    NAKOUTE         4       //
01285 #define    NAKINE          6       //
01286 #define    FLERRE          7       //
01287 
01288 /* UEDATX -  */
01289 #define    UEDATX_0        0       //
01290 #define    UEDATX_1        1       //
01291 #define    UEDATX_2        2       //
01292 #define    UEDATX_3        3       //
01293 #define    UEDATX_4        4       //
01294 #define    UEDATX_5        5       //
01295 #define    UEDATX_6        6       //
01296 #define    UEDATX_7        7       //
01297 
01298 /* UEBCLX -  */
01299 #define    UEBCLX_0        0       //
01300 #define    UEBCLX_1        1       //
01301 #define    UEBCLX_2        2       //
01302 #define    UEBCLX_3        3       //
01303 #define    UEBCLX_4        4       //
01304 #define    UEBCLX_5        5       //
01305 #define    UEBCLX_6        6       //
01306 #define    UEBCLX_7        7       //
01307 
01308 /* UEBCHX -  */
01309 #define    UEBCHX_0        0       //
01310 #define    UEBCHX_1        1       //
01311 #define    UEBCHX_2        2       //
01312 
01313 /* UEINT -  */
01314 #define    UEINT_0         0       //
01315 #define    UEINT_1         1       //
01316 #define    UEINT_2         2       //
01317 #define    UEINT_3         3       //
01318 #define    UEINT_4         4       //
01319 #define    UEINT_5         5       //
01320 #define    UEINT_6         6       //
01321 
01322 
01323 /* ***** USB_GLOBAL ******************* */
01324 /* UHWCON - USB Hardware Configuration Register */
01325 #define    UVREGE          0       //
01326 #define    UVCONE          4       //
01327 #define    UIDE            6       //
01328 #define    UIMOD           7       //
01329 
01330 /* USBCON - USB General Control Register */
01331 #define    VBUSTE          0       //
01332 #define    IDTE            1       //
01333 #define    OTGPADE         4       //
01334 #define    FRZCLK          5       //
01335 #define    HOST            6       //
01336 #define    USBE            7       //
01337 
01338 /* USBSTA -  */
01339 #define    VBUS            0       //
01340 #define    ID              1       //
01341 #define    SPEED1          3       //
01342 
01343 /* USBINT -  */
01344 #define    VBUSTI          0       //
01345 #define    IDTI            1       //
01346 
01347 
01348 /* OTGCON -  */
01349 #define    VBUSRQC         0       //
01350 #define    VBUSREQ         1       //
01351 #define    VBUSHWC         2       //
01352 #define    SRPSEL          3       //
01353 #define    SRPREQ          4       //
01354 #define    HNPREQ          5       //
01355 
01356 /* OTGIEN -  */
01357 #define    SRPE            0       //
01358 #define    VBERRE          1       //
01359 #define    BCERRE          2       //
01360 #define    ROLEEXE         3       //
01361 #define    HNPERRE         4       //
01362 #define    STOE            5       //
01363 
01364 /* OTGINT -  */
01365 #define    SRPI            0       //
01366 #define    VBERRI          1       //
01367 #define    BCERRI          2       //
01368 #define    ROLEEXI         3       //
01369 #define    HNPERRI         4       //
01370 #define    STOI            5       //
01371 
01372 
01373 /* ***** USB_HOST ********************* */
01374 /* UHCON -  */
01375 #define    SOFEN           0       //
01376 #define    RESET           1       //
01377 #define    RESUME          2       //
01378 
01379 /* UHINT -  */
01380 #define    DCONNI          0       //
01381 #define    DDISCI          1       //
01382 #define    RSTI            2       //
01383 #define    RSMEDI          3       //
01384 #define    RXRSMI          4       //
01385 #define    HSOFI           5       //
01386 #define    HWUPI           6       //
01387 
01388 /* UHIEN -  */
01389 #define    HWUPE           6
01390 #define    HSOFE           5
01391 #define    RXRSME          4
01392 #define    RSMEDE          3
01393 #define    RSTE            2
01394 #define    DDISCE          1
01395 #define    DCONNE          0
01396 
01397 
01398 
01399 /* UHADDR -  */
01400 #define    UHADDR_0        0       //
01401 #define    UHADDR_1        1       //
01402 #define    UHADDR_2        2       //
01403 #define    UHADDR_3        3       //
01404 #define    UHADDR_4        4       //
01405 #define    UHADDR_5        5       //
01406 #define    UHADDR_6        6       //
01407 
01408 /* UHFNUMH -  */
01409 #define    UHFNUMH_0       0       //
01410 #define    UHFNUMH_1       1       //
01411 #define    UHFNUMH_2       2       //
01412 
01413 /* UHFNUML -  */
01414 #define    UHFNUML_0       0       //
01415 #define    UHFNUML_1       1       //
01416 #define    UHFNUML_2       2       //
01417 #define    UHFNUML_3       3       //
01418 #define    UHFNUML_4       4       //
01419 #define    UHFNUML_5       5       //
01420 #define    UHFNUML_6       6       //
01421 #define    UHFNUML_7       7       //
01422 
01423 /* UHFLEN -  */
01424 #define    UHFLEN_0        0       //
01425 #define    UHFLEN_1        1       //
01426 #define    UHFLEN_2        2       //
01427 #define    UHFLEN_3        3       //
01428 #define    UHFLEN_4        4       //
01429 #define    UHFLEN_5        5       //
01430 #define    UHFLEN_6        6       //
01431 #define    UHFLEN_7        7       //
01432 
01433 /* UPINRQX -  */
01434 #define    INRQ0           0       //
01435 #define    INRQ1           1       //
01436 #define    INRQ2           2       //
01437 #define    INRQ3           3       //
01438 #define    INRQ4           4       //
01439 #define    INRQ5           5       //
01440 #define    INRQ6           6       //
01441 #define    INRQ7           7       //
01442 
01443 /* UPINTX -  */
01444 #define    RXINI           0       //
01445 #define    RXSTALLI        1       //
01446 #define    TXOUTI          2       //
01447 #define    TXSTPI          3       //
01448 #define    PERRI           4       //
01449 //#define  RWAL            5       //
01450 #define    NAKEDI          6       //
01451 //#define  FIFOCON         7       //
01452 
01453 /* UPNUM -  */
01454 #define    PNUM0           0       //
01455 #define    PNUM1           1       //
01456 #define    PNUM2           2       //
01457 
01458 /* UPRST -  */
01459 #define    PRST0           0       //
01460 #define    PRST1           1       //
01461 #define    PRST2           2       //
01462 #define    PRST3           3       //
01463 #define    PRST4           4       //
01464 #define    PRST5           5       //
01465 #define    PRST6           6       //
01466 
01467 /* UPCONX -  */
01468 #define    PEN             0       //
01469 //#define  RSTDT           3       //
01470 #define    INMODE          5       //
01471 #define    PFREEZE         6       //
01472 
01473 /* UPCFG0X -  */
01474 #define    PEPNUM0         0       //
01475 #define    PEPNUM1         1       //
01476 #define    PEPNUM2         2       //
01477 #define    PEPNUM3         3       //
01478 #define    PTOKEN0         4       //
01479 #define    PTOKEN1         5       //
01480 #define    PTYPE0          6       //
01481 #define    PTYPE1          7       //
01482 
01483 /* UPCFG1X -  */
01484 //#define  ALLOC           1       //
01485 #define    PBK0            2       //
01486 #define    PBK1            3       //
01487 #define    PSIZE0          4       //
01488 #define    PSIZE1          5       //
01489 #define    PSIZE2          6       //
01490 
01491 /* UPSTAX -  */
01492 #define    NBUSYK0         0       //
01493 #define    NBUSYK1         1       //
01494 //#define  DTSEQ0          2       //
01495 //#define  DTSEQ1          3       //
01496 //#define  UNDERFI         5       //
01497 //#define  OVERFI          6       //
01498 //#define  CFGOK           7       //
01499 
01500 /* UPCFG2X -  */
01501 /* USB_HOST/UPCFG2X/BIT0: Name missing */
01502 /* USB_HOST/UPCFG2X/BIT1: Name missing */
01503 /* USB_HOST/UPCFG2X/BIT2: Name missing */
01504 /* USB_HOST/UPCFG2X/BIT3: Name missing */
01505 /* USB_HOST/UPCFG2X/BIT4: Name missing */
01506 /* USB_HOST/UPCFG2X/BIT5: Name missing */
01507 /* USB_HOST/UPCFG2X/BIT6: Name missing */
01508 /* USB_HOST/UPCFG2X/BIT7: Name missing */
01509 
01510 /* UPIENX -  */
01511 #define    RXINE           0       //
01512 #define    RXSTALLE        1       //
01513 #define    TXOUTE          2       //
01514 #define    TXSTPE          3       //
01515 #define    PERRE           4       //
01516 #define    NAKEDE          6       //
01517 //#define  FLERRE          7       //
01518 
01519 /* UPDATX -  */
01520 #define    PDAT0           0       //
01521 #define    PDAT1           1       //
01522 #define    PDAT2           2       //
01523 #define    PDAT3           3       //
01524 #define    PDAT4           4       //
01525 #define    PDAT5           5       //
01526 #define    PDAT6           6       //
01527 #define    PDAT7           7       //
01528 
01529 /* UPBCLX -  */
01530 #define    PBYCT0          0       //
01531 #define    PBYCT1          1       //
01532 #define    PBYCT2          2       //
01533 #define    PBYCT3          3       //
01534 #define    PBYCT4          4       //
01535 #define    PBYCT5          5       //
01536 #define    PBYCT6          6       //
01537 #define    PBYCT7          7       //
01538 
01539 /* UPBCHX -  */
01540 #define    PBYCT8          0       //
01541 #define    PBYCT9          1       //
01542 #define    PBYCT10         2       //
01543 
01544 /* UPINT -  */
01545 #define    PINT0           0       //
01546 #define    PINT1           1       //
01547 #define    PINT2           2       //
01548 #define    PINT3           3       //
01549 #define    PINT4           4       //
01550 #define    PINT5           5       //
01551 #define    PINT6           6       //
01552 
01553 /* UPERRX -  */
01554 #define    DATATGL         0       //
01555 #define    DATAPID         1       //
01556 #define    PID             2       //
01557 #define    TIMEOUT         3       //
01558 #define    CRC16           4       //
01559 #define    COUNTER0        5       //
01560 #define    COUNTER1        6       //
01561 
01562 /* Pointer definition */
01563 #define    XL     r26
01564 #define    XH     r27
01565 #define    YL     r28
01566 #define    YH     r29
01567 #define    ZL     r30
01568 #define    ZH     r31
01569 
01570 
01571 // registers PLLCSR
01572 #define    PLLP2     4  
01573 #define    PLLP1     3
01574 #define    PLLP0     2
01575 #define    PLLE      1
01576 #define    PLOCK     0
01577 
01578 
01579 
01580 
01581 #endif  /* _MCU_H*/
01582 
01583 
01584 
01585 
01586 
01587 
01588 
01589 
01590 
01591 
01592 
01593 
01594 
01595 

Generated on Fri Mar 17 16:02:03 2006 for Atmel by  doxygen 1.4.6-NO