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00016 #ifndef _USB_DRV_H_
00017 #define _USB_DRV_H_
00018
00019
00020
00021
00022 typedef enum endpoint_parameter{ep_num, ep_type, ep_direction, ep_size, ep_bank, nyet_status} t_endpoint_parameter;
00023
00027
00028
00029
00030 #define MAX_EP_NB 7
00031
00032 #define EP_CONTROL 0
00033 #define EP_1 1
00034 #define EP_2 2
00035 #define EP_3 3
00036 #define EP_4 4
00037 #define EP_5 5
00038 #define EP_6 6
00039 #define EP_7 7
00040
00041 #define PIPE_CONTROL 0
00042 #define PIPE_0 0
00043 #define PIPE_1 1
00044 #define PIPE_2 2
00045 #define PIPE_3 3
00046 #define PIPE_4 4
00047 #define PIPE_5 5
00048 #define PIPE_6 6
00049 #define PIPE_7 7
00050
00051
00052 #define MSK_EP_DIR 0x7F
00053 #define MSK_UADD 0x7F
00054 #define MSK_EPTYPE 0xC0
00055 #define MSK_EPSIZE 0x70
00056 #define MSK_EPBK 0x0C
00057 #define MSK_DTSEQ 0x0C
00058 #define MSK_NBUSYBK 0x03
00059 #define MSK_CURRBK 0x03
00060 #define MSK_DAT 0xFF // UEDATX
00061 #define MSK_BYCTH 0x07 // UEBCHX
00062 #define MSK_BYCTL 0xFF // UEBCLX
00063 #define MSK_EPINT 0x7F // UEINT
00064 #define MSK_HADDR 0xFF // UHADDR
00065
00066
00067 #define MSK_PNUM 0x07 // UPNUM
00068 #define MSK_PRST 0x7F // UPRST
00069 #define MSK_PTYPE 0xC0 // UPCFG0X
00070 #define MSK_PTOKEN 0x30
00071 #define MSK_PEPNUM 0x0F
00072 #define MSK_PSIZE 0x70 // UPCFG1X
00073 #define MSK_PBK 0x0C
00074
00075 #define MSK_NBUSYBK 0x03
00076
00077 #define MSK_ERROR 0x1F
00078
00079 #define MSK_PTYPE 0xC0 // UPCFG0X
00080 #define MSK_PTOKEN 0x30
00081 #define MSK_TOKEN_SETUP 0x30
00082 #define MSK_TOKEN_IN 0x10
00083 #define MSK_TOKEN_OUT 0x20
00084 #define MSK_PEPNUM 0x0F
00085
00086 #define MSK_PSIZE 0x70 // UPCFG1X
00087 #define MSK_PBK 0x0C
00088
00089
00090
00091
00092 #define TYPE_CONTROL 0
00093 #define TYPE_ISOCHRONOUS 1
00094 #define TYPE_BULK 2
00095 #define TYPE_INTERRUPT 3
00096
00097
00098 #define DIRECTION_OUT 0
00099 #define DIRECTION_IN 1
00100
00101
00102 #define SIZE_8 0
00103 #define SIZE_16 1
00104 #define SIZE_32 2
00105 #define SIZE_64 3
00106 #define SIZE_128 4
00107 #define SIZE_256 5
00108 #define SIZE_512 6
00109 #define SIZE_1024 7
00110
00111
00112
00113 #define ONE_BANK 0
00114 #define TWO_BANKS 1
00115
00116
00117 #define NYET_ENABLED 0
00118 #define NYET_DISABLED 1
00119
00120
00121 #define TOKEN_SETUP 0
00122 #define TOKEN_IN 1
00123 #define TOKEN_OUT 2
00124
00125
00126
00127
00131 #define Usb_build_ep_config0(type, dir, nyet) ((type<<6) | (nyet<<1) | (dir))
00132 #define Usb_build_ep_config1(size, bank ) ((size<<4) | (bank<<2) )
00133 #define usb_configure_endpoint(num, type, dir, size, bank, nyet) \
00134 ( Usb_select_endpoint(num), \
00135 usb_config_ep(Usb_build_ep_config0(type, dir, nyet),\
00136 Usb_build_ep_config1(size, bank) ))
00137
00138 #define Host_build_pipe_config0(type, token, ep_num) ((type<<6) | (token<<4) | (ep_num))
00139 #define Host_build_pipe_config1(size, bank ) ((size<<4) | (bank<<2) )
00140 #define host_configure_pipe(num, type, token,ep_num, size, bank, freq) \
00141 ( Host_select_pipe(num), \
00142 Host_set_interrupt_frequency(freq), \
00143 host_config_pipe(Host_build_pipe_config0(type, token, ep_num),\
00144 Host_build_pipe_config1(size, bank) ))
00145
00146
00151 #define Usb_enable_regulator() (UHWCON |= (1<<UVREGE))
00152
00153 #define Usb_disable_regulator() (UHWCON &= ~(1<<UVREGE))
00154
00155 #define Is_usb_regulator_enabled() ((UHWCON & (1<<UVREGE)) ? TRUE : FALSE)
00156
00157
00162 #define Usb_enable_uid_pin() (UHWCON |= (1<<UIDE))
00163
00164 #define Usb_disable_uid_pin() (UHWCON &= ~(1<<UIDE))
00165
00166 #define Usb_force_device_mode() (Usb_disable_uid_pin(), UHWCON |= (1<<UIMOD))
00167
00168 #define Usb_force_host_mode() (Usb_disable_uid_pin(), UHWCON &= ~(1<<UIMOD))
00169
00170 #define Usb_enable_uvcon_pin() (UHWCON |= (1<<UVCONE))
00171
00172 #define Usb_disable_uvcon_pin() (UHWCON &= ~(1<<UVCONE))
00173
00174 #define Usb_full_speed_mode() (UHWCON |= (1<<UDSS))
00175
00176 #define Usb_low_speed_mode() (UHWCON &= ~(1<<UDSS))
00177
00179 #define Usb_enable() (USBCON |= ((1<<USBE) | (1<<OTGPADE)))
00180
00181 #define Usb_disable() (USBCON &= ~((1<<USBE) | (1<<OTGPADE)))
00182 #define Is_usb_enabled() ((USBCON & (1<<USBE)) ? TRUE : FALSE)
00183
00185 #define Usb_enable_vbus_pad() (USBCON |= (1<<OTGPADE))
00186
00187 #define Usb_disable_vbus_pad() (USBCON &= ~(1<<OTGPADE))
00188
00189 #define Usb_select_device() (USBCON &= ~(1<<HOST))
00190 #define Usb_select_host() (USBCON |= (1<<HOST))
00191 #define Is_usb_host_enabled() ((USBCON & (1<<HOST)) ? TRUE : FALSE)
00192
00194 #define Usb_freeze_clock() (USBCON |= (1<<FRZCLK))
00195 #define Usb_unfreeze_clock() (USBCON &= ~(1<<FRZCLK))
00196 #define Is_usb_clock_freezed() ((USBCON & (1<<FRZCLK)) ? TRUE : FALSE)
00197
00198 #define Usb_enable_id_interrupt() (USBCON |= (1<<IDTE))
00199 #define Usb_disable_id_interrupt() (USBCON &= ~(1<<IDTE))
00200 #define Is_usb_id_interrupt_enabled() ((USBCON & (1<<IDTE)) ? TRUE : FALSE)
00201 #define Is_usb_id_device() ((USBSTA & (1<<ID)) ? TRUE : FALSE)
00202 #define Usb_ack_id_transition() (USBINT = ~(1<<IDTI))
00203 #define Is_usb_id_transition() ((USBINT & (1<<IDTI)) ? TRUE : FALSE)
00204
00205 #define Usb_enable_vbus_interrupt() (USBCON |= (1<<VBUSTE))
00206 #define Usb_disable_vbus_interrupt() (USBCON &= ~(1<<VBUSTE))
00207 #define Is_usb_vbus_interrupt_enabled() ((USBCON & (1<<VBUSTE)) ? TRUE : FALSE)
00208 #define Is_usb_vbus_high() ((USBSTA & (1<<VBUS)) ? TRUE : FALSE)
00209 #define Is_usb_vbus_low() ((USBSTA & (1<<VBUS)) ? FALSE : TRUE)
00210 #define Usb_ack_vbus_transition() (USBINT = ~(1<<VBUSTI))
00211 #define Is_usb_vbus_transition() ((USBINT & (1<<VBUSTI)) ? TRUE : FALSE)
00212
00214 #define Usb_get_general_interrupt() (USBINT & (USBCON & MSK_IDTE_VBUSTE))
00215
00216 #define Usb_ack_all_general_interrupt() (USBINT = ~(USBCON & MSK_IDTE_VBUSTE))
00217 #define Usb_ack_cache_id_transition(x) ((x) &= ~(1<<IDTI))
00218 #define Usb_ack_cache_vbus_transition(x) ((x) &= ~(1<<VBUSTI))
00219 #define Is_usb_cache_id_transition(x) (((x) & (1<<IDTI)) )
00220 #define Is_usb_cache_vbus_transition(x) (((x) & (1<<VBUSTI)))
00221
00223 #define Usb_get_otg_interrupt() (OTGINT & OTGIEN)
00224
00225 #define Usb_ack_all_otg_interrupt() (OTGINT = ~OTGIEN)
00226 #define Is_otg_cache_bconnection_error(x) (((x) & MSK_BCERRI))
00227 #define Usb_ack_cache_bconnection_error(x) ((x) &= ~MSK_BCERRI)
00228
00229 #define Usb_enter_dpram_mode() (UDPADDH = (1<<DPACC))
00230 #define Usb_exit_dpram_mode() (UDPADDH = (U8)~(1<<DPACC))
00231 #define Usb_set_dpram_address(addr) (UDPADDH = (1<<DPACC) + ((Uint16)addr >> 8), UDPADDL = (Uchar)addr)
00232 #define Usb_write_dpram_byte(val) (UEDATX=val)
00233 #define Usb_read_dpram_byte() (UEDATX)
00234
00236 #define Usb_enable_vbus() (OTGCON |= (1<<VBUSREQ))
00237
00238 #define Usb_disable_vbus() (OTGCON |= (1<<VBUSRQC))
00239
00240 #define Usb_enable_manual_vbus() (PORTE|=0x80,DDRE|=0x80,Usb_disable_uvcon_pin())
00241
00243 #define Usb_device_initiate_hnp() (OTGCON |= (1<<HNPREQ))
00244
00245 #define Usb_host_accept_hnp() (OTGCON |= (1<<HNPREQ))
00246
00247 #define Usb_host_reject_hnp() (OTGCON &= ~(1<<HNPREQ))
00248
00249 #define Usb_device_initiate_srp() (OTGCON |= (1<<SRPREQ))
00250
00251 #define Usb_select_vbus_srp_method() (OTGCON |= (1<<SRPSEL))
00252
00253 #define Usb_select_data_srp_method() (OTGCON &= ~(1<<SRPSEL))
00254
00255 #define Usb_enable_vbus_hw_control() (OTGCON &= ~(1<<VBUSHWC))
00256
00257 #define Usb_disable_vbus_hw_control() (OTGCON |= (1<<VBUSHWC))
00258
00259 #define Is_usb_vbus_enabled() ((OTGCON & (1<<VBUSREQ)) ? TRUE : FALSE)
00260
00261 #define Is_usb_hnp() ((OTGCON & (1<<HNPREQ)) ? TRUE : FALSE)
00262
00263 #define Is_usb_device_srp() ((OTGCON & (1<<SRPREQ)) ? TRUE : FALSE)
00264
00266 #define Usb_enable_suspend_time_out_interrupt() (OTGIEN |= (1<<STOE))
00267
00268 #define Usb_disable_suspend_time_out_interrupt() (OTGIEN &= ~(1<<STOE))
00269 #define Is_suspend_time_out_interrupt_enabled() ((OTGIEN & (1<<STOE)) ? TRUE : FALSE)
00270
00271 #define Usb_ack_suspend_time_out_interrupt() (OTGINT &= ~(1<<STOI))
00272
00273 #define Is_usb_suspend_time_out_interrupt() ((OTGINT & (1<<STOI)) ? TRUE : FALSE)
00274
00276 #define Usb_enable_hnp_error_interrupt() (OTGIEN |= (1<<HNPERRE))
00277
00278 #define Usb_disable_hnp_error_interrupt() (OTGIEN &= ~(1<<HNPERRE))
00279 #define Is_hnp_error_interrupt_enabled() ((OTGIEN & (1<<HNPERRE)) ? TRUE : FALSE)
00280
00281 #define Usb_ack_hnp_error_interrupt() (OTGINT &= ~(1<<HNPERRI))
00282
00283 #define Is_usb_hnp_error_interrupt() ((OTGINT & (1<<HNPERRI)) ? TRUE : FALSE)
00284
00286 #define Usb_enable_role_exchange_interrupt() (OTGIEN |= (1<<ROLEEXE))
00287
00288 #define Usb_disable_role_exchange_interrupt() (OTGIEN &= ~(1<<ROLEEXE))
00289 #define Is_role_exchange_interrupt_enabled() ((OTGIEN & (1<<ROLEEXE)) ? TRUE : FALSE)
00290
00291 #define Usb_ack_role_exchange_interrupt() (OTGINT &= ~(1<<ROLEEXI))
00292
00293 #define Is_usb_role_exchange_interrupt() ((OTGINT & (1<<ROLEEXI)) ? TRUE : FALSE)
00294
00296 #define Usb_enable_bconnection_error_interrupt() (OTGIEN |= (1<<BCERRE))
00297
00298 #define Usb_disable_bconnection_error_interrupt() (OTGIEN &= ~(1<<BCERRE))
00299 #define Is_bconnection_error_interrupt_enabled() ((OTGIEN & (1<<BCERRE)) ? TRUE : FALSE)
00300
00301 #define Usb_ack_bconnection_error_interrupt() (OTGINT &= ~(1<<BCERRI))
00302
00303 #define Is_usb_bconnection_error_interrupt() ((OTGINT & (1<<BCERRI)) ? TRUE : FALSE)
00304
00306 #define Usb_enable_vbus_error_interrupt() (OTGIEN |= (1<<VBERRE))
00307
00308 #define Usb_disable_vbus_error_interrupt() (OTGIEN &= ~(1<<VBERRE))
00309 #define Is_vbus_error_interrupt_enabled() ((OTGIEN & (1<<VBERRE)) ? TRUE : FALSE)
00310
00311 #define Usb_ack_vbus_error_interrupt() (OTGINT &= ~(1<<VBERRI))
00312
00313 #define Is_usb_vbus_error_interrupt() ((OTGINT & (1<<VBERRI)) ? TRUE : FALSE)
00314
00316 #define Usb_enable_srp_interrupt() (OTGIEN |= (1<<SRPE))
00317
00318 #define Usb_disable_srp_interrupt() (OTGIEN &= ~(1<<SRPE))
00319 #define Is_srp_interrupt_enabled() ((OTGIEN & (1<<SRPE)) ? TRUE : FALSE)
00320
00321 #define Usb_ack_srp_interrupt() (OTGINT &= ~(1<<SRPI))
00322
00323 #define Is_usb_srp_interrupt() ((OTGINT & (1<<SRPI)) ? TRUE : FALSE)
00324
00325
00326
00331 #define Usb_initiate_remote_wake_up() (UDCON |= (1<<RMWKUP))
00332
00333 #define Usb_detach() (UDCON |= (1<<DETACH))
00334
00335 #define Usb_attach() (UDCON &= ~(1<<DETACH))
00336
00337 #define Is_usb_pending_remote_wake_up() ((UDCON & (1<<RMWKUP)) ? TRUE : FALSE)
00338
00339 #define Is_usb_detached() ((UDCON & (1<<DETACH)) ? TRUE : FALSE)
00340
00342 #define Usb_get_device_interrupt() (UDINT & (1<<UDIEN))
00343
00344 #define Usb_ack_all_device_interrupt() (UDINT = ~(1<<UDIEN))
00345
00347 #define Usb_enable_remote_wake_up_interrupt() (UDIEN |= (1<<UPRSME))
00348
00349 #define Usb_disable_remote_wake_up_interrupt() (UDIEN &= ~(1<<UPRSME))
00350 #define Is_remote_wake_up_interrupt_enabled() ((UDIEN & (1<<UPRSME)) ? TRUE : FALSE)
00351
00352 #define Usb_ack_remote_wake_up_start() (UDINT = ~(1<<UPRSMI))
00353
00354 #define Is_usb_remote_wake_up_start() ((UDINT & (1<<UPRSMI)) ? TRUE : FALSE)
00355
00357 #define Usb_enable_resume_interrupt() (UDIEN |= (1<<EORSME))
00358
00359 #define Usb_disable_resume_interrupt() (UDIEN &= ~(1<<EORSME))
00360 #define Is_resume_interrupt_enabled() ((UDIEN & (1<<EORSME)) ? TRUE : FALSE)
00361
00362 #define Usb_ack_resume() (UDINT = ~(1<<EORSMI))
00363
00364 #define Is_usb_resume() ((UDINT & (1<<EORSMI)) ? TRUE : FALSE)
00365
00367 #define Usb_enable_wake_up_interrupt() (UDIEN |= (1<<WAKEUPE))
00368
00369 #define Usb_disable_wake_up_interrupt() (UDIEN &= ~(1<<WAKEUPE))
00370 #define Is_swake_up_interrupt_enabled() ((UDIEN & (1<<WAKEUPE)) ? TRUE : FALSE)
00371
00372 #define Usb_ack_wake_up() (UDINT = ~(1<<WAKEUPI))
00373
00374 #define Is_usb_wake_up() ((UDINT & (1<<WAKEUPI)) ? TRUE : FALSE)
00375
00377 #define Usb_enable_reset_interrupt() (UDIEN |= (1<<EORSTE))
00378
00379 #define Usb_disable_reset_interrupt() (UDIEN &= ~(1<<EORSTE))
00380 #define Is_reset_interrupt_enabled() ((UDIEN & (1<<EORSTE)) ? TRUE : FALSE)
00381
00382 #define Usb_ack_reset() (UDINT = ~(1<<EORSTI))
00383
00384 #define Is_usb_reset() ((UDINT & (1<<EORSTI)) ? TRUE : FALSE)
00385
00387 #define Usb_enable_sof_interrupt() (UDIEN |= (1<<SOFE))
00388
00389 #define Usb_disable_sof_interrupt() (UDIEN &= ~(1<<SOFE))
00390 #define Is_sof_interrupt_enabled() ((UDIEN & (1<<SOFE)) ? TRUE : FALSE)
00391
00392 #define Usb_ack_sof() (UDINT = ~(1<<SOFI))
00393
00394 #define Is_usb_sof() ((UDINT & (1<<SOFI)) ? TRUE : FALSE)
00395
00397 #define Usb_enable_suspend_interrupt() (UDIEN |= (1<<SUSPE))
00398
00399 #define Usb_disable_suspend_interrupt() (UDIEN &= ~(1<<SUSPE))
00400 #define Is_suspend_interrupt_enabled() ((UDIEN & (1<<SUSPE)) ? TRUE : FALSE)
00401
00402 #define Usb_ack_suspend() (UDINT = ~(1<<SUSPI))
00403
00404 #define Is_usb_suspend() ((UDINT & (1<<SUSPI)) ? TRUE : FALSE)
00405
00407 #define Usb_enable_address() (UDADDR |= (1<<ADDEN))
00408
00409 #define Usb_disable_address() (UDADDR &= ~(1<<ADDEN))
00410
00411 #define Usb_configure_address(addr) (UDADDR = (UDADDR & (1<<ADDEN)) | ((U8)addr & MSK_UADD))
00412
00414 #define Usb_frame_number() ((U16)((((U16)UDFNUMH) << 8) | ((U16)UDFNUML)))
00415
00416 #define Is_usb_frame_number_crc_error() ((UDMFN & (1<<FNCERR)) ? TRUE : FALSE)
00417
00418
00419
00420
00421
00426 #define Usb_select_endpoint(ep) (UENUM = (U8)ep )
00427
00429 #define Usb_reset_endpoint(ep) (UERST = 1 << (U8)ep, UERST = 0)
00430
00432 #define Usb_enable_endpoint() (UECONX |= (1<<EPEN))
00433
00434 #define Usb_enable_stall_handshake() (UECONX |= (1<<STALLRQ))
00435
00436 #define Usb_reset_data_toggle() (UECONX |= (1<<RSTDT))
00437
00438 #define Usb_disable_endpoint() (UECONX &= ~(1<<EPEN))
00439
00440 #define Usb_disable_stall_handshake() (UECONX |= (1<<STALLRQC))
00441
00442 #define Usb_select_epnum_for_cpu() (UECONX &= ~(1<<EPNUMS))
00443
00444 #define Is_usb_endpoint_enabled() ((UECONX & (1<<EPEN)) ? TRUE : FALSE)
00445
00446 #define Is_usb_endpoint_stall_requested() ((UECONX & (1<<STALLRQ)) ? TRUE : FALSE)
00447
00449 #define Usb_configure_endpoint_type(type) (UECFG0X = (UECFG0X & ~(MSK_EPTYPE)) | ((U8)type << 6))
00450
00451 #define Usb_configure_endpoint_direction(dir) (UECFG0X = (UECFG0X & ~(1<<EPDIR)) | ((U8)dir))
00452
00454 #define Usb_configure_endpoint_size(size) (UECFG1X = (UECFG1X & ~MSK_EPSIZE) | ((U8)size << 4))
00455
00456 #define Usb_configure_endpoint_bank(bank) (UECFG1X = (UECFG1X & ~MSK_EPBK) | ((U8)bank << 2))
00457
00458 #define Usb_allocate_memory() (UECFG1X |= (1<<ALLOC))
00459
00460 #define Usb_unallocate_memory() (UECFG1X &= ~(1<<ALLOC))
00461
00463 #define Usb_ack_overflow_interrupt() (UESTA0X &= ~(1<<OVERFI))
00464
00465 #define Usb_ack_underflow_interrupt() (UESTA0X &= ~(1<<UNDERFI))
00466
00467 #define Usb_ack_zlp() (UESTA0X &= ~(1<<ZLPSEEN))
00468
00469 #define Usb_data_toggle() ((UESTA0X&MSK_DTSEQ) >> 2)
00470
00471 #define Usb_nb_busy_bank() (UESTA0X & MSK_NBUSYBK)
00472
00473 #define Is_usb_one_bank_busy() ((UESTA0X & MSK_NBUSYBK) == 0 ? FALSE : TRUE)
00474
00475 #define Is_endpoint_configured() ((UESTA0X & (1<<CFGOK)) ? TRUE : FALSE)
00476
00477 #define Is_usb_overflow() ((UESTA0X & (1<<OVERFI)) ? TRUE : FALSE)
00478
00479 #define Is_usb_underflow() ((UESTA0X & (1<<UNDERFI)) ? TRUE : FALSE)
00480
00481 #define Is_usb_zlp() ((UESTA0X & (1<<ZLPSEEN)) ? TRUE : FALSE)
00482
00484 #define Usb_control_direction() ((UESTA1X & (1<<CTRLDIR)) >> 2)
00485
00486 #define Usb_current_bank() ( UESTA1X & MSK_CURRBK)
00487
00489 #define Usb_ack_fifocon() (UEINTX &= ~(1<<FIFOCON))
00490
00491 #define Usb_ack_nak_in() (UEINTX &= ~(1<<NAKINI))
00492
00493 #define Usb_ack_nak_out() (UEINTX &= ~(1<<NAKOUTI))
00494
00495 #define Usb_ack_receive_setup() (UEINTX &= ~(1<<RXSTPI))
00496
00497 #define Usb_ack_receive_out() (UEINTX &= ~(1<<RXOUTI), Usb_ack_fifocon())
00498
00499 #define Usb_ack_stalled() (MSK_STALLEDI= 0)
00500
00501 #define Usb_ack_in_ready() (UEINTX &= ~(1<<TXINI), Usb_ack_fifocon())
00502
00503 #define Usb_kill_last_in_bank() (UENTTX |= (1<<RXOUTI))
00504
00505 #define Is_usb_read_enabled() (UEINTX&(1<<RWAL))
00506
00507 #define Is_usb_write_enabled() (UEINTX&(1<<RWAL))
00508
00509 #define Is_usb_read_control_enabled() (UEINTX&(1<<TXINI))
00510
00511 #define Is_usb_receive_setup() (UEINTX&(1<<RXSTPI))
00512
00513 #define Is_usb_receive_out() (UEINTX&(1<<RXOUTI))
00514
00515 #define Is_usb_in_ready() (UEINTX&(1<<TXINI))
00516
00517 #define Usb_send_in() (UEINTX &= ~(1<<FIFOCON))
00518
00519 #define Usb_send_control_in() (UEINTX &= ~(1<<TXINI))
00520
00521 #define Usb_free_out_bank() (UEINTX &= ~(1<<FIFOCON))
00522
00523 #define Usb_ack_control_out() (UEINTX &= ~(1<<RXOUTI))
00524
00526 #define Usb_enable_flow_error_interrupt() (UEIENX |= (1<<FLERRE))
00527
00528 #define Usb_enable_nak_in_interrupt() (UEIENX |= (1<<NAKINE))
00529
00530 #define Usb_enable_nak_out_interrupt() (UEIENX |= (1<<NAKOUTE))
00531
00532 #define Usb_enable_receive_setup_interrupt() (UEIENX |= (1<<RXSTPE))
00533
00534 #define Usb_enable_receive_out_interrupt() (UEIENX |= (1<<RXOUTE))
00535
00536 #define Usb_enable_stalled_interrupt() (UEIENX |= (1<<STALLEDE))
00537
00538 #define Usb_enable_in_ready_interrupt() (UEIENX |= (1<<TXIN))
00539
00540 #define Usb_disable_flow_error_interrupt() (UEIENX &= ~(1<<FLERRE))
00541
00542 #define Usb_disable_nak_in_interrupt() (UEIENX &= ~(1<<NAKINE))
00543
00544 #define Usb_disable_nak_out_interrupt() (UEIENX &= ~(1<<NAKOUTE))
00545
00546 #define Usb_disable_receive_setup_interrupt() (UEIENX &= ~(1<<RXSTPE))
00547
00548 #define Usb_disable_receive_out_interrupt() (UEIENX &= ~(1<<RXOUTE))
00549
00550 #define Usb_disable_stalled_interrupt() (UEIENX &= ~(1<<STALLEDE))
00551
00552 #define Usb_disable_in_ready_interrupt() (UEIENX &= ~(1<<TXIN))
00553
00555 #define Usb_read_byte() (UEDATX)
00556
00557 #define Usb_write_byte(byte) (UEDATX = (U8)byte)
00558
00560 #define Usb_byte_counter() ((((U16)UEBCHX) << 8) | (UEBCLX))
00561
00562 #define Usb_byte_counter_8() ((U8)UEBCLX)
00563
00565 #define Usb_interrupt_flags() (UEINT != 0x00)
00566
00567 #define Is_usb_endpoint_event() (Usb_interrupt_flags())
00568
00569
00570 #define Usb_select_ep_for_cpu(ep) (Usb_select_epnum_for_cpu(), Usb_select_endpoint(ep))
00571
00573
00574
00575
00580 #define Host_allocate_memory() (UPCFG1X |= (1<<ALLOC))
00581
00582 #define Host_unallocate_memory() (UPCFG1X &= ~(1<<ALLOC))
00583
00585 #define Host_enable() (USBCON |= (1<<HOST))
00586
00587 #define Host_enable_sof() (UHCON |= (1<<SOFEN))
00588
00589 #define Host_disable_sof() (UHCON &= ~(1<<SOFEN))
00590
00591 #define Host_send_reset() (UHCON |= (1<<RESET))
00592
00593 #define Host_is_reset() ((UHCON & (1<<RESET)) ? TRUE : FALSE)
00594
00595 #define Host_send_resume() (UHCON |= (1<<RESUME))
00596
00597 #define Host_is_resume() ((UHCON & (1<<RESUME)) ? TRUE : FALSE)
00598
00600 #define Host_enable_sof_interrupt() (UHIEN |= (1<<HSOFE))
00601
00602 #define Host_disable_sof_interrupt() (UHIEN &= ~(1<<HSOFE))
00603 #define Is_host_sof_interrupt_enabled() ((UHIEN & (1<<HSOFE)) ? TRUE : FALSE)
00604
00605 #define Host_is_sof() ((UHINT & (1<<HSOFI)) ? TRUE : FALSE)
00606 #define Is_host_sof() ((UHINT & (1<<HSOFI)) ? TRUE : FALSE)
00607 #define Host_ack_sof() (UHINT &= ~(1<<HSOFI))
00608
00610 #define Host_enable_hwup_interrupt() (UHIEN |= (1<<HWUPE))
00611
00612 #define Host_disable_hwup_interrupt() (UHIEN &= ~(1<<HWUPE))
00613 #define Is_host_hwup_interrupt_enabled() ((UHIEN & (1<<HWUPE)) ? TRUE : FALSE)
00614
00615 #define Host_is_hwup() ((UHINT & (1<<HWUPI)) ? TRUE : FALSE)
00616
00617 #define Is_host_hwup() ((UHINT & (1<<HWUPI)) ? TRUE : FALSE)
00618 #define Host_ack_hwup() (UHINT &= ~(1<<HWUPI))
00619
00621 #define Host_enable_down_stream_resume_interrupt() (UHIEN |= (1<<RSMEDE))
00622
00623 #define Host_disable_down_stream_resume_interrupt() (UHIEN &= ~(1<<RSMEDE))
00624 #define Is_host_down_stream_resume_interrupt_enabled() ((UHIEN & (1<<RSMEDE)) ? TRUE : FALSE)
00625
00626 #define Is_host_down_stream_resume() ((UHINT & (1<<RSMEDI)) ? TRUE : FALSE)
00627 #define Host_ack_down_stream_resume() (UHINT &= ~(1<<RSMEDI))
00628
00630 #define Host_enable_remote_wakeup_interrupt() (UHIEN |= (1<<RXRSME))
00631
00632 #define Host_disable_remote_wakeup_interrupt() (UHIEN &= ~(1<<RXRSME))
00633 #define Is_host_remote_wakeup_interrupt_enabled() ((UHIEN & (1<<RXRSME)) ? TRUE : FALSE)
00634
00635 #define Host_is_remote_wakeup() ((UHINT & (1<<RXRSMI)) ? TRUE : FALSE)
00636
00637 #define Is_host_remote_wakeup() ((UHINT & (1<<RXRSMI)) ? TRUE : FALSE)
00638 #define Host_ack_remote_wakeup() (UHINT &= ~(1<<RXRSMI))
00639
00641 #define Host_enable_device_connection_interrupt() (UHIEN |= (1<<DCONNE))
00642
00643 #define Host_disable_device_connection_interrupt() (UHIEN &= ~(1<<DCONNE))
00644 #define Is_host_device_connection_interrupt_enabled() ((UHIEN & (1<<DCONNE)) ? TRUE : FALSE)
00645
00646 #define Is_device_connection() (UHINT & (1<<DCONNI))
00647
00648 #define Host_ack_device_connection() (UHINT = ~(1<<DCONNI))
00649
00651 #define Host_enable_device_disconnection_interrupt() (UHIEN |= (1<<DDISCE))
00652
00653 #define Host_disable_device_disconnection_interrupt() (UHIEN &= ~(1<<DDISCE))
00654 #define Is_host_device_disconnection_interrupt_enabled() ((UHIEN & (1<<DDISCE)) ? TRUE : FALSE)
00655
00656 #define Is_device_disconnection() (UHINT & (1<<DDISCI) ? TRUE : FALSE)
00657
00658 #define Host_ack_device_disconnection() (UHINT = ~(1<<DDISCI))
00659
00661 #define Host_enable_reset_interrupt() (UHIEN |= (1<<RSTE))
00662
00663 #define Host_disable_reset_interrupt() (UHIEN &= ~(1<<RSTE))
00664 #define Is_host_reset_interrupt_enabled() ((UHIEN & (1<<RSTE)) ? TRUE : FALSE)
00665
00666 #define Host_ack_reset() (UHINT = ~(1<<RSTI))
00667
00668 #define Is_host_reset() Host_is_reset()
00669
00670
00672 #define Host_vbus_request() (OTGCON |= (1<<VBUSREQ))
00673
00674 #define Host_clear_vbus_request() (OTGCON |= (1<<VBUSRQC))
00675
00676 #define Host_configure_address(addr) (UHADDR = addr & MSK_HADDR)
00677
00678
00679
00680
00685 #define Host_select_pipe(p) (UPNUM = (U8)p)
00686
00688 #define Host_enable_pipe() (UPCONX |= (1<<PEN))
00689
00690 #define Host_disable_pipe() (UPCONX &= ~(1<<PEN))
00691
00693 #define Host_set_token_setup() (UPCFG0X = UPCFG0X & ~MSK_TOKEN_SETUP)
00694
00695 #define Host_set_token_in() (UPCFG0X = (UPCFG0X & ~MSK_TOKEN_SETUP) | MSK_TOKEN_IN)
00696
00697 #define Host_set_token_out() (UPCFG0X = (UPCFG0X & ~MSK_TOKEN_SETUP) | MSK_TOKEN_OUT)
00698
00700 #define Host_get_endpoint_number() (UPCFG0X & (1<<MSK_PEPNUM))
00701
00703 #define Host_set_interrupt_frequency(frq) (UPCFG2X = (U8)frq)
00704
00706 #define Is_pipe_configured() (UPSTAX & (1<<CFGOK))
00707
00708 #define Is_host_one_bank_busy() ((UPSTAX & (1<<MSK_NBUSYBK)) != 0)
00709
00710 #define Host_number_of_busy_bank() (UPSTAX & (1<<MSK_NBUSYBK))
00711
00713 #define Host_reset_pipe(p) (UPRST = 1<<p , UPRST = 0)
00714
00716 #define Host_write_byte(dat) (UPDATX = dat)
00717
00718 #define Host_read_byte() (UPDATX)
00719
00721 #define Host_freeze_pipe() (UPCONX |= (1<<PFREEZE))
00722
00723 #define Host_unfreeze_pipe() (UPCONX &= ~(1<<PFREEZE))
00724
00725 #define Is_host_pipe_freeze() (UPCONX & (1<<PFREEZE))
00726
00728 #define Host_reset_pipe_data_toggle() (UPCONX |= (1<<RSTDT) )
00729
00731 #define Is_host_setup_sent() ((UPINTX & (1<<TXSTPI)) ? TRUE : FALSE)
00732
00733 #define Is_host_control_in_received() ((UPINTX & (1<<RXINI)) ? TRUE : FALSE)
00734
00735 #define Is_host_control_out_sent() ((UPINTX & (1<<TXOUTI)) ? TRUE : FALSE)
00736
00737 #define Is_host_stall() ((UPINTX & (1<<RXSTALLI)) ? TRUE : FALSE)
00738
00739 #define Is_host_pipe_error() ((UPINTX & (1<<PERRI)) ? TRUE : FALSE)
00740
00741 #define Host_send_setup() (UPINTX &= ~(1<<FIFOCON))
00742
00743 #define Host_send_control_in() (UPINTX &= ~(1<<FIFOCON))
00744
00745 #define Host_send_control_out() (UPINTX &= ~(1<<FIFOCON))
00746
00747 #define Host_ack_control_out() (UPINTX &= ~(1<<TXOUTI))
00748
00749 #define Host_ack_control_in() (UPINTX &= ~(1<<RXINI))
00750
00751 #define Host_ack_setup() (UPINTX &= ~(1<<TXOUTI))
00752
00753 #define Host_ack_stall() (UPINTX &= ~(1<<RXSTALLI))
00754
00756 #define Host_send_out() (UPINTX = 0x7B)
00757
00758 #define Is_host_out_sent() ((UPINTX & (1<<TXOUTI)) ? TRUE : FALSE)
00759
00760 #define Host_ack_out_sent() (UPINTX = 0xFB)
00761
00762 #define Is_host_in_received() ((UPINTX & (1<<FIFOCON)) ? TRUE : FALSE)
00763
00764 #define Host_ack_in_received() (UPINTX = 0x7E)
00765
00767 #define Is_host_read_enabled() (UPINTX&(1<<RWAL))
00768
00769 #define Is_host_write_enabled() (UPINTX&(1<<RWAL))
00770
00772 #define Host_standard_in_mode() (UPCONX &= ~(1<<INMODE))
00773
00774 #define Host_continuous_in_mode() (UPCONX |= (1<<INMODE))
00775
00777 #define Host_in_request_number(in_num) (UPINRQX = (U8)in_num)
00778
00779 #define Host_get_in_request_number() (UPINRQX)
00780
00782 #define Host_data_length_U8() (UPBCLX)
00783
00784 #define Host_data_length_U16() ((((U16)UPBCHX)<<8) | UPBCLX)
00785
00786 #define Host_byte_counter() Host_data_length_U16()
00787
00788 #define Host_byte_counter_8() Host_data_length_U8()
00789
00791 #define Host_get_pipe_length() ((U16)0x08 << ((UPCFG1X & MSK_PSIZE)>>4))
00792
00794 #define Host_error_status() (UPERRX & MSK_ERROR)
00795
00796 #define Host_ack_all_errors() (UPERRX = 0x00)
00797
00799 #define Host_enable_transmit_interrupt() (UPIENX |= (1<<TXOUTE))
00800
00801 #define Host_disable_transmit_interrupt() (UPIENX &= ~(1<<TXOUTE))
00802
00804 #define Host_enable_receive_interrupt() (UPIENX |= (1<<RXINE))
00805
00806 #define Host_disable_receive_interrupt() (UPIENX &= ~(1<<RXINE))
00807
00808 #define Get_pipe_token(x) ((x & (0x80)) ? TOKEN_IN : TOKEN_OUT)
00809
00810 #define Host_set_device_supported() (device_status |= 0x01)
00811 #define Host_clear_device_supported() (device_status &= ~0x01)
00812 #define Is_host_device_supported() (device_status & 0x01)
00813
00814 #define Host_set_device_ready() (device_status |= 0x02)
00815 #define Host_clear_device_ready() (device_status &= ~0x02)
00816 #define Is_host_device_ready() (device_status & 0x02)
00817
00818 #define Host_set_configured() (device_status |= 0x04)
00819 #define Host_clear_configured() (device_status &= ~0x04)
00820 #define Is_host_configured() (device_status & 0x04)
00821
00822 #define Host_clear_device_status() (device_status = 0x00)
00823
00824
00831
00832 #define wSWAP(x) \
00833 ( (((x)>>8)&0x00FF) \
00834 | (((x)<<8)&0xFF00) \
00835 )
00836
00837
00845 #if !defined(BIG_ENDIAN) && !defined(LITTLE_ENDIAN)
00846 #error YOU MUST Define the Endian Type of target: LITTLE_ENDIAN or BIG_ENDIAN
00847 #endif
00848 #ifdef LITTLE_ENDIAN
00849 #define Usb_write_word_enum_struc(x) (x)
00850 #else //BIG_ENDIAN
00851 #define Usb_write_word_enum_struc(x) (wSWAP(x))
00852 #endif
00853
00854
00856
00857
00858
00859 U8 usb_config_ep (U8, U8);
00860 U8 usb_select_enpoint_interrupt (void);
00861 U16 usb_get_nb_byte_epw (void);
00862 U8 usb_send_packet (U8 , U8*, U8);
00863 U8 usb_read_packet (U8 , U8*, U8);
00864 void usb_halt_endpoint (U8);
00865 void usb_reset_endpoint (U8);
00866 U8 usb_init_device (void);
00867
00868 U8 host_config_pipe (U8, U8);
00869 U8 host_determine_pipe_size (U16);
00870 void host_disable_all_pipe (void);
00871
00872 #endif // _USB_DRV_H_
00873