ioAT90USB1287.h

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00001 /****** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** */
00002 /****** Created: 2005-11-29 12:56 ******* Source: AT90USB1287.xml ********* */
00003 /**************************************************************************
00004  *
00005  * - File Name          : "ioAT90USB1287.h"
00006  * - Title              : Register/Bit Definitions for the AT90USB1287
00007  * - Date               : 2005-11-29
00008  * - Version            : 2.20
00009  * - Support E-Mail     : avr@atmel.com
00010  * - Target MCU         : AT90USB1287
00011  *
00012  * - Compiler           : GNU AVRGCC
00013  *
00014  **************************************************************************
00015  */
00016 
00017 #ifndef _IOAT90USB1287_H_
00018 #define _IOAT90USB1287_H_
00019 
00020 
00021 
00022 /* ***** SPECIFY DEVICE *************************************************** */
00023 #define    PART_NAME       AT90USB1287
00024 #define    SIGNATURE_000   0x1e
00025 #define    SIGNATURE_001   0x97
00026 #define    SIGNATURE_002   0x82
00027 
00028 
00029 
00030 /* ***** I/O REGISTER DEFINITIONS ***************************************** */
00031 /* NOTE:
00032  * Definitions marked "MEMORY MAPPED"are extended I/O ports
00033  * and cannot be used with IN/OUT instructions
00034  */
00035 #define    PLLCSR          _SFR_IO8(0x29)
00036 #define    TESTPADSTATUS   _SFR_MEM8(0xfd)
00037 #define    TESTPADPULL     _SFR_MEM8(0xfe)
00038 #define    TESTPADCTRL     _SFR_MEM8(0xff)
00039 #define    UPERRX          _SFR_MEM8(0xf5)
00040 #define    UEINT           _SFR_MEM8(0xf4)
00041 #define    UPINT           _SFR_MEM8(0xf8)
00042 #define    UEBCHX          _SFR_MEM8(0xf3)
00043 #define    UPBCHX          _SFR_MEM8(0xf7)
00044 #define    UEBCLX          _SFR_MEM8(0xf2)
00045 #define    UPBCLX          _SFR_MEM8(0xf6)
00046 #define    UEDATX          _SFR_MEM8(0xf1)
00047 #define    UPDATX          _SFR_MEM8(0xaf)
00048 #define    UEIENX          _SFR_MEM8(0xf0)
00049 #define    UPIENX          _SFR_MEM8(0xae)
00050 #define    UESTA1X         _SFR_MEM8(0xef)
00051 #define    UPCFG2X         _SFR_MEM8(0xad)
00052 #define    UESTA0X         _SFR_MEM8(0xee)
00053 #define    UPSTAX          _SFR_MEM8(0xac)
00054 #define    UECFG1X         _SFR_MEM8(0xed)
00055 #define    UPCFG1X         _SFR_MEM8(0xab)
00056 #define    UECFG0X         _SFR_MEM8(0xec)
00057 #define    UPCFG0X         _SFR_MEM8(0xaa)
00058 #define    UECONX          _SFR_MEM8(0xeb)
00059 #define    UPCONX          _SFR_MEM8(0xa9)
00060 #define    UERST           _SFR_MEM8(0xea)
00061 #define    UPRST           _SFR_MEM8(0xa8)
00062 #define    UENUM           _SFR_MEM8(0xe9)
00063 #define    UPNUM           _SFR_MEM8(0xa7)
00064 #define    UEINTX          _SFR_MEM8(0xe8)
00065 #define    UPINTX          _SFR_MEM8(0xa6)
00066 #define    UDTST           _SFR_MEM8(0xe7)
00067 #define    UPINRQX         _SFR_MEM8(0xa5)
00068 #define    UDMFN           _SFR_MEM8(0xe6)
00069 #define    UHFLEN          _SFR_MEM8(0xa4)
00070 #define    UDFNUMH         _SFR_MEM8(0xe5)
00071 #define    UHFNUMH         _SFR_MEM8(0xa3)
00072 #define    UDFNUML         _SFR_MEM8(0xe4)
00073 #define    UHFNUML         _SFR_MEM8(0xa2)
00074 #define    UDADDR          _SFR_MEM8(0xe3)
00075 #define    UHADDR          _SFR_MEM8(0xa1)
00076 #define    UDIEN           _SFR_MEM8(0xe2)
00077 #define    UHIEN           _SFR_MEM8(0xa0)
00078 #define    UDINT           _SFR_MEM8(0xe1)
00079 #define    UHINT           _SFR_MEM8(0x9f)
00080 #define    UDCON           _SFR_MEM8(0xe0)
00081 #define    UHCON           _SFR_MEM8(0x9e)
00082 #define    OTGINT          _SFR_MEM8(0xdf)
00083 #define    OTGIEN          _SFR_MEM8(0xde)
00084 #define    OTGCON          _SFR_MEM8(0xdd)
00085 #define    OTGTCON         _SFR_MEM8(0xf9)
00086 #define    UDPADDH         _SFR_MEM8(0xdc)
00087 #define    UDPADDL         _SFR_MEM8(0xdb)
00088 #define    USBINT          _SFR_MEM8(0xda)
00089 #define    USBSTA          _SFR_MEM8(0xd9)
00090 #define    USBCON          _SFR_MEM8(0xd8)
00091 #define    UHWCON          _SFR_MEM8(0xd7)
00092 #define    UCSR2B          _SFR_MEM8(0xd1)
00093 #define    UCSR2A          _SFR_MEM8(0xd0)
00094 #define    UDR1            _SFR_MEM8(0xce)
00095 #define    UBRR1           _SFR_MEM16(0xcc)
00096 #define    UCSR1C          _SFR_MEM8(0xca)
00097 #define    UCSR1B          _SFR_MEM8(0xc9)
00098 #define    UCSR1A          _SFR_MEM8(0xc8)
00099 #define    TWAMR           _SFR_MEM8(0xbd)
00100 #define    TWCR            _SFR_MEM8(0xbc)
00101 #define    TWDR            _SFR_MEM8(0xbb)
00102 #define    TWAR            _SFR_MEM8(0xba)
00103 #define    TWSR            _SFR_MEM8(0xb9)
00104 #define    TWBR            _SFR_MEM8(0xb8)
00105 #define    ASSR            _SFR_MEM8(0xb6)
00106 #define    OCR2B           _SFR_MEM8(0xb4)
00107 #define    OCR2A           _SFR_MEM8(0xb3)
00108 #define    TCNT2           _SFR_MEM8(0xb2)
00109 #define    TCCR2B          _SFR_MEM8(0xb1)
00110 #define    TCCR2A          _SFR_MEM8(0xb0)
00111 #define    OCR4CH          _SFR_MEM8(0xad)
00112 #define    OCR4CL          _SFR_MEM8(0xac)
00113 #define    OCR4BH          _SFR_MEM8(0xab)
00114 #define    OCR4BL          _SFR_MEM8(0xaa)
00115 #define    OCR4AH          _SFR_MEM8(0xa9)
00116 #define    OCR4AL          _SFR_MEM8(0xa8)
00117 #define    ICR4H           _SFR_MEM8(0xa7)
00118 #define    ICR4L           _SFR_MEM8(0xa6)
00119 #define    TCNT4H          _SFR_MEM8(0xa5)
00120 #define    TCNT4L          _SFR_MEM8(0xa4)
00121 #define    TCCR4C          _SFR_MEM8(0xa2)
00122 #define    TCCR4B          _SFR_MEM8(0xa1)
00123 #define    TCCR4A          _SFR_MEM8(0xa0)
00124 #define    OCR3C           _SFR_MEM16(0x9c)
00125 #define    OCR3B           _SFR_MEM16(0x9a)
00126 #define    OCR3A           _SFR_MEM16(0x98)
00127 #define    ICR3            _SFR_MEM16(0x96)
00128 #define    TCNT3           _SFR_MEM16(0x94)
00129 #define    TCCR3C          _SFR_MEM8(0x92)
00130 #define    TCCR3B          _SFR_MEM8(0x91)
00131 #define    TCCR3A          _SFR_MEM8(0x90)
00132 #define    OCR1C           _SFR_MEM16(0x8c)
00133 #define    OCR1B           _SFR_MEM16(0x8a)
00134 #define    OCR1A           _SFR_MEM16(0x88)
00135 #define    ICR1            _SFR_MEM16(0x86)
00136 #define    TCNT1           _SFR_MEM16(0x84)
00137 #define    TCCR1C          _SFR_MEM8(0x82)
00138 #define    TCCR1B          _SFR_MEM8(0x81)
00139 #define    TCCR1A          _SFR_MEM8(0x80)
00140 #define    DIDR1           _SFR_MEM8(0x7f)
00141 #define    DIDR0           _SFR_MEM8(0x7e)
00142 #define    DIDR2           _SFR_MEM8(0x7d)
00143 #define    ADMUX           _SFR_MEM8(0x7c)
00144 #define    ADCSRB          _SFR_MEM8(0x7b)
00145 #define    ADCSRA          _SFR_MEM8(0x7a)
00146 #define    ADCH            _SFR_MEM8(0x79)
00147 #define    ADCL            _SFR_MEM8(0x78)
00148 #define    XMCRB           _SFR_MEM8(0x75)
00149 #define    XMCRA           _SFR_MEM8(0x74)
00150 #define    TIMSK5          _SFR_MEM8(0x73)
00151 #define    TIMSK4          _SFR_MEM8(0x72)
00152 #define    TIMSK3          _SFR_MEM8(0x71)
00153 #define    TIMSK2          _SFR_MEM8(0x70)
00154 #define    TIMSK1          _SFR_MEM8(0x6f)
00155 #define    TIMSK0          _SFR_MEM8(0x6e)
00156 #define    PCMSK2          _SFR_MEM8(0x6d)
00157 #define    PCMSK1          _SFR_MEM8(0x6c)
00158 #define    PCMSK0          _SFR_MEM8(0x6b)
00159 #define    EICRB           _SFR_MEM8(0x6a)
00160 #define    EICRA           _SFR_MEM8(0x69)
00161 #define    PCICR           _SFR_MEM8(0x68)
00162 #define    OSCCAL          _SFR_MEM8(0x66)
00163 #define    PRR1            _SFR_MEM8(0x65)
00164 #define    PRR0            _SFR_MEM8(0x64)
00165 #define    CLKPR           _SFR_MEM8(0x61)
00166 #define    WDTCSR          _SFR_MEM8(0x60)
00167 #define    SREG            _SFR_IO8(0x3f)
00168 #define    SP              _SFR_IO16(0x3d)
00169 #define    EIND            _SFR_IO8(0x3c)
00170 #define    RAMPZ           _SFR_IO8(0x3b)
00171 #define    SPMCSR          _SFR_IO8(0x37)
00172 #define    MCUCR           _SFR_IO8(0x35)
00173 #define    MCUSR           _SFR_IO8(0x34)
00174 #define    SMCR            _SFR_IO8(0x33)
00175 #define    OCDR            _SFR_IO8(0x31)
00176 #define    ACSR            _SFR_IO8(0x30)
00177 #define    SPDR            _SFR_IO8(0x2e)
00178 #define    SPSR            _SFR_IO8(0x2d)
00179 #define    SPCR            _SFR_IO8(0x2c)
00180 #define    GPIOR2          _SFR_IO8(0x2b)
00181 #define    GPIOR1          _SFR_IO8(0x2a)
00182 #define    OCR0B           _SFR_IO8(0x28)
00183 #define    OCR0A           _SFR_IO8(0x27)
00184 #define    TCNT0           _SFR_IO8(0x26)
00185 #define    TCCR0B          _SFR_IO8(0x25)
00186 #define    TCCR0A          _SFR_IO8(0x24)
00187 #define    GTCCR           _SFR_IO8(0x23)
00188 #define    EEARH           _SFR_IO8(0x22)
00189 #define    EEARL           _SFR_IO8(0x21)
00190 #define    EEDR            _SFR_IO8(0x20)
00191 #define    EECR            _SFR_IO8(0x1f)
00192 #define    GPIOR0          _SFR_IO8(0x1e)
00193 #define    EIMSK           _SFR_IO8(0x1d)
00194 #define    EIFR            _SFR_IO8(0x1c)
00195 #define    PCIFR           _SFR_IO8(0x1b)
00196 #define    TIFR5           _SFR_IO8(0x1a)
00197 #define    TIFR4           _SFR_IO8(0x19)
00198 #define    TIFR3           _SFR_IO8(0x18)
00199 #define    TIFR2           _SFR_IO8(0x17)
00200 #define    TIFR1           _SFR_IO8(0x16)
00201 #define    TIFR0           _SFR_IO8(0x15)
00202 #define    PORTF           _SFR_IO8(0x11)
00203 #define    DDRF            _SFR_IO8(0x10)
00204 #define    PINF            _SFR_IO8(0x0f)
00205 #define    PORTE           _SFR_IO8(0x0e)
00206 #define    DDRE            _SFR_IO8(0x0d)
00207 #define    PINE            _SFR_IO8(0x0c)
00208 #define    PORTD           _SFR_IO8(0x0b)
00209 #define    DDRD            _SFR_IO8(0x0a)
00210 #define    PIND            _SFR_IO8(0x09)
00211 #define    PORTC           _SFR_IO8(0x08)
00212 #define    DDRC            _SFR_IO8(0x07)
00213 #define    PINC            _SFR_IO8(0x06)
00214 #define    PORTB           _SFR_IO8(0x05)
00215 #define    DDRB            _SFR_IO8(0x04)
00216 #define    PINB            _SFR_IO8(0x03)
00217 #define    PORTA           _SFR_IO8(0x02)
00218 #define    DDRA            _SFR_IO8(0x01)
00219 #define    PINA            _SFR_IO8(0x00)
00220 
00221 
00222 /* ***** BIT DEFINITIONS ************************************************** */
00223 
00224 #define    CLKPCE          7
00225 
00226 /* ***** WATCHDOG ********************* */
00227 /* WDTCSR - Watchdog Timer Control Register */
00228 #define    WDP0            0       // Watch Dog Timer Prescaler bit 0
00229 #define    WDP1            1       // Watch Dog Timer Prescaler bit 1
00230 #define    WDP2            2       // Watch Dog Timer Prescaler bit 2
00231 #define    WDE             3       // Watch Dog Enable
00232 #define    WDCE            4       // Watchdog Change Enable
00233 #define    WDP3            5       // Watchdog Timer Prescaler Bit 3
00234 #define    WDIE            6       // Watchdog Timeout Interrupt Enable
00235 #define    WDIF            7       // Watchdog Timeout Interrupt Flag
00236 
00237 
00238 /* ***** PORTA ************************ */
00239 /* PORTA - Port A Data Register */
00240 #define    PORTA0          0       // Port A Data Register bit 0
00241 #define    PORTA1          1       // Port A Data Register bit 1
00242 #define    PORTA2          2       // Port A Data Register bit 2
00243 #define    PORTA3          3       // Port A Data Register bit 3
00244 #define    PORTA4          4       // Port A Data Register bit 4
00245 #define    PORTA5          5       // Port A Data Register bit 5
00246 #define    PORTA6          6       // Port A Data Register bit 6
00247 #define    PORTA7          7       // Port A Data Register bit 7
00248 
00249 /* DDRA - Port A Data Direction Register */
00250 #define    DDA0            0       // Data Direction Register, Port A, bit 0
00251 #define    DDA1            1       // Data Direction Register, Port A, bit 1
00252 #define    DDA2            2       // Data Direction Register, Port A, bit 2
00253 #define    DDA3            3       // Data Direction Register, Port A, bit 3
00254 #define    DDA4            4       // Data Direction Register, Port A, bit 4
00255 #define    DDA5            5       // Data Direction Register, Port A, bit 5
00256 #define    DDA6            6       // Data Direction Register, Port A, bit 6
00257 #define    DDA7            7       // Data Direction Register, Port A, bit 7
00258 
00259 /* PINA - Port A Input Pins */
00260 #define    PINA0           0       // Input Pins, Port A bit 0
00261 #define    PINA1           1       // Input Pins, Port A bit 1
00262 #define    PINA2           2       // Input Pins, Port A bit 2
00263 #define    PINA3           3       // Input Pins, Port A bit 3
00264 #define    PINA4           4       // Input Pins, Port A bit 4
00265 #define    PINA5           5       // Input Pins, Port A bit 5
00266 #define    PINA6           6       // Input Pins, Port A bit 6
00267 #define    PINA7           7       // Input Pins, Port A bit 7
00268 
00269 
00270 /* ***** PORTB ************************ */
00271 /* PORTB - Port B Data Register */
00272 #define    PORTB0          0       // Port B Data Register bit 0
00273 #define    PORTB1          1       // Port B Data Register bit 1
00274 #define    PORTB2          2       // Port B Data Register bit 2
00275 #define    PORTB3          3       // Port B Data Register bit 3
00276 #define    PORTB4          4       // Port B Data Register bit 4
00277 #define    PORTB5          5       // Port B Data Register bit 5
00278 #define    PORTB6          6       // Port B Data Register bit 6
00279 #define    PORTB7          7       // Port B Data Register bit 7
00280 
00281 /* DDRB - Port B Data Direction Register */
00282 #define    DDB0            0       // Port B Data Direction Register bit 0
00283 #define    DDB1            1       // Port B Data Direction Register bit 1
00284 #define    DDB2            2       // Port B Data Direction Register bit 2
00285 #define    DDB3            3       // Port B Data Direction Register bit 3
00286 #define    DDB4            4       // Port B Data Direction Register bit 4
00287 #define    DDB5            5       // Port B Data Direction Register bit 5
00288 #define    DDB6            6       // Port B Data Direction Register bit 6
00289 #define    DDB7            7       // Port B Data Direction Register bit 7
00290 
00291 /* PINB - Port B Input Pins */
00292 #define    PINB0           0       // Port B Input Pins bit 0
00293 #define    PINB1           1       // Port B Input Pins bit 1
00294 #define    PINB2           2       // Port B Input Pins bit 2
00295 #define    PINB3           3       // Port B Input Pins bit 3
00296 #define    PINB4           4       // Port B Input Pins bit 4
00297 #define    PINB5           5       // Port B Input Pins bit 5
00298 #define    PINB6           6       // Port B Input Pins bit 6
00299 #define    PINB7           7       // Port B Input Pins bit 7
00300 
00301 
00302 /* ***** PORTC ************************ */
00303 /* PORTC - Port C Data Register */
00304 #define    PORTC0          0       // Port C Data Register bit 0
00305 #define    PORTC1          1       // Port C Data Register bit 1
00306 #define    PORTC2          2       // Port C Data Register bit 2
00307 #define    PORTC3          3       // Port C Data Register bit 3
00308 #define    PORTC4          4       // Port C Data Register bit 4
00309 #define    PORTC5          5       // Port C Data Register bit 5
00310 #define    PORTC6          6       // Port C Data Register bit 6
00311 #define    PORTC7          7       // Port C Data Register bit 7
00312 
00313 /* DDRC - Port C Data Direction Register */
00314 #define    DDC0            0       // Port C Data Direction Register bit 0
00315 #define    DDC1            1       // Port C Data Direction Register bit 1
00316 #define    DDC2            2       // Port C Data Direction Register bit 2
00317 #define    DDC3            3       // Port C Data Direction Register bit 3
00318 #define    DDC4            4       // Port C Data Direction Register bit 4
00319 #define    DDC5            5       // Port C Data Direction Register bit 5
00320 #define    DDC6            6       // Port C Data Direction Register bit 6
00321 #define    DDC7            7       // Port C Data Direction Register bit 7
00322 
00323 /* PINC - Port C Input Pins */
00324 #define    PINC0           0       // Port C Input Pins bit 0
00325 #define    PINC1           1       // Port C Input Pins bit 1
00326 #define    PINC2           2       // Port C Input Pins bit 2
00327 #define    PINC3           3       // Port C Input Pins bit 3
00328 #define    PINC4           4       // Port C Input Pins bit 4
00329 #define    PINC5           5       // Port C Input Pins bit 5
00330 #define    PINC6           6       // Port C Input Pins bit 6
00331 #define    PINC7           7       // Port C Input Pins bit 7
00332 
00333 
00334 /* ***** PORTD ************************ */
00335 /* PORTD - Port D Data Register */
00336 #define    PORTD0          0       // Port D Data Register bit 0
00337 #define    PORTD1          1       // Port D Data Register bit 1
00338 #define    PORTD2          2       // Port D Data Register bit 2
00339 #define    PORTD3          3       // Port D Data Register bit 3
00340 #define    PORTD4          4       // Port D Data Register bit 4
00341 #define    PORTD5          5       // Port D Data Register bit 5
00342 #define    PORTD6          6       // Port D Data Register bit 6
00343 #define    PORTD7          7       // Port D Data Register bit 7
00344 
00345 /* DDRD - Port D Data Direction Register */
00346 #define    DDD0            0       // Port D Data Direction Register bit 0
00347 #define    DDD1            1       // Port D Data Direction Register bit 1
00348 #define    DDD2            2       // Port D Data Direction Register bit 2
00349 #define    DDD3            3       // Port D Data Direction Register bit 3
00350 #define    DDD4            4       // Port D Data Direction Register bit 4
00351 #define    DDD5            5       // Port D Data Direction Register bit 5
00352 #define    DDD6            6       // Port D Data Direction Register bit 6
00353 #define    DDD7            7       // Port D Data Direction Register bit 7
00354 
00355 /* PIND - Port D Input Pins */
00356 #define    PIND0           0       // Port D Input Pins bit 0
00357 #define    PIND1           1       // Port D Input Pins bit 1
00358 #define    PIND2           2       // Port D Input Pins bit 2
00359 #define    PIND3           3       // Port D Input Pins bit 3
00360 #define    PIND4           4       // Port D Input Pins bit 4
00361 #define    PIND5           5       // Port D Input Pins bit 5
00362 #define    PIND6           6       // Port D Input Pins bit 6
00363 #define    PIND7           7       // Port D Input Pins bit 7
00364 
00365 
00366 /* ***** PORTE ************************ */
00367 /* PORTE - Data Register, Port E */
00368 #define    PORTE0          0       // 
00369 #define    PORTE1          1       // 
00370 #define    PORTE2          2       // 
00371 #define    PORTE3          3       // 
00372 #define    PORTE4          4       // 
00373 #define    PORTE5          5       // 
00374 #define    PORTE6          6       // 
00375 #define    PORTE7          7       // 
00376 
00377 /* DDRE - Data Direction Register, Port E */
00378 #define    DDE0            0       // 
00379 #define    DDE1            1       // 
00380 #define    DDE2            2       // 
00381 #define    DDE3            3       // 
00382 #define    DDE4            4       // 
00383 #define    DDE5            5       // 
00384 #define    DDE6            6       // 
00385 #define    DDE7            7       // 
00386 
00387 /* PINE - Input Pins, Port E */
00388 #define    PINE0           0       // 
00389 #define    PINE1           1       // 
00390 #define    PINE2           2       // 
00391 #define    PINE3           3       // 
00392 #define    PINE4           4       // 
00393 #define    PINE5           5       // 
00394 #define    PINE6           6       // 
00395 #define    PINE7           7       // 
00396 
00397 
00398 /* ***** PORTF ************************ */
00399 /* PORTF - Data Register, Port F */
00400 #define    PORTF0          0       // 
00401 #define    PORTF1          1       // 
00402 #define    PORTF2          2       // 
00403 #define    PORTF3          3       // 
00404 #define    PORTF4          4       // 
00405 #define    PORTF5          5       // 
00406 #define    PORTF6          6       // 
00407 #define    PORTF7          7       // 
00408 
00409 /* DDRF - Data Direction Register, Port F */
00410 #define    DDF0            0       // 
00411 #define    DDF1            1       // 
00412 #define    DDF2            2       // 
00413 #define    DDF3            3       // 
00414 #define    DDF4            4       // 
00415 #define    DDF5            5       // 
00416 #define    DDF6            6       // 
00417 #define    DDF7            7       // 
00418 
00419 /* PINF - Input Pins, Port F */
00420 #define    PINF0           0       // 
00421 #define    PINF1           1       // 
00422 #define    PINF2           2       // 
00423 #define    PINF3           3       // 
00424 #define    PINF4           4       // 
00425 #define    PINF5           5       // 
00426 #define    PINF6           6       // 
00427 #define    PINF7           7       // 
00428 
00429 
00430 /* ***** CPU ************************** */
00431 /* SREG - Status Register */
00432 #define    SREG_C          0       // Carry Flag
00433 #define    SREG_Z          1       // Zero Flag
00434 #define    SREG_N          2       // Negative Flag
00435 #define    SREG_V          3       // Two's Complement Overflow Flag
00436 #define    SREG_S          4
00437 #define    SREG_H          5       // Half Carry Flag
00438 #define    SREG_T          6       // Bit Copy Storage
00439 #define    SREG_I          7       // Global Interrupt Enable
00440 
00441 /* MCUCR - MCU Control Register */
00442 #define    IVCE            0       // Interrupt Vector Change Enable
00443 #define    IVSEL           1       // Interrupt Vector Select
00444 #define    PUD             4       // Pull-up disable
00445 #define    JTD             7       // JTAG Interface Disable
00446 
00447 /* MCUSR - MCU Status Register */
00448 #define    PORF            0       // Power-on reset flag
00449 #define    EXTRF           1       // External Reset Flag
00450 #define    BORF            2       // Brown-out Reset Flag
00451 #define    WDRF            3       // Watchdog Reset Flag
00452 #define    JTRF            4       // JTAG Reset Flag
00453 
00454 /* XMCRA - External Memory Control Register A */
00455 #define    SRW00           0       // Wait state select bit lower page
00456 #define    SRW01           1       // Wait state select bit lower page
00457 #define    SRW10           2       // Wait state select bit upper page
00458 #define    SRW11           3       // Wait state select bit upper page
00459 #define    SRL0            4       // Wait state page limit
00460 #define    SRL1            5       // Wait state page limit
00461 #define    SRL2            6       // Wait state page limit
00462 #define    SRE             7       // External SRAM Enable
00463 
00464 /* XMCRB - External Memory Control Register B */
00465 #define    XMM0            0       // External Memory High Mask
00466 #define    XMM1            1       // External Memory High Mask
00467 #define    XMM2            2       // External Memory High Mask
00468 #define    XMBK            7       // External Memory Bus Keeper Enable
00469 
00470 /* OSCCAL - Oscillator Calibration Value */
00471 #define    CAL0            0       // Oscillator Calibration Value Bit0
00472 #define    CAL1            1       // Oscillator Calibration Value Bit1
00473 #define    CAL2            2       // Oscillator Calibration Value Bit2
00474 #define    CAL3            3       // Oscillator Calibration Value Bit3
00475 #define    CAL4            4       // Oscillator Calibration Value Bit4
00476 #define    CAL5            5       // Oscillator Calibration Value Bit5
00477 #define    CAL6            6       // Oscillator Calibration Value Bit6
00478 #define    CAL7            7       // Oscillator Calibration Value Bit7
00479 
00480 /* CLKPR -  */
00481 #define    CLKPS0          0       // 
00482 #define    CLKPS1          1       // 
00483 #define    CLKPS2          2       // 
00484 #define    CLKPS3          3       // 
00485 #define    CPKPCE          7       // 
00486 
00487 /* SMCR - Sleep Mode Control Register */
00488 #define    SE              0       // Sleep Enable
00489 #define    SM0             1       // Sleep Mode Select bit 0
00490 #define    SM1             2       // Sleep Mode Select bit 1
00491 #define    SM2             3       // Sleep Mode Select bit 2
00492 
00493 /* RAMPZ - RAM Page Z Select Register */
00494 #define    RAMPZ0          0       // RAM Page Z Select Register Bit 0
00495 
00496 /* EIND - Extended Indirect Register */
00497 #define    EIND0           0       // Bit 0
00498 
00499 /* GPIOR2 - General Purpose IO Register 2 */
00500 #define    GPIOR20         0       // General Purpose IO Register 2 bit 0
00501 #define    GPIOR21         1       // General Purpose IO Register 2 bit 1
00502 #define    GPIOR22         2       // General Purpose IO Register 2 bit 2
00503 #define    GPIOR23         3       // General Purpose IO Register 2 bit 3
00504 #define    GPIOR24         4       // General Purpose IO Register 2 bit 4
00505 #define    GPIOR25         5       // General Purpose IO Register 2 bit 5
00506 #define    GPIOR26         6       // General Purpose IO Register 2 bit 6
00507 #define    GPIOR27         7       // General Purpose IO Register 2 bit 7
00508 
00509 /* GPIOR1 - General Purpose IO Register 1 */
00510 #define    GPIOR10         0       // General Purpose IO Register 1 bit 0
00511 #define    GPIOR11         1       // General Purpose IO Register 1 bit 1
00512 #define    GPIOR12         2       // General Purpose IO Register 1 bit 2
00513 #define    GPIOR13         3       // General Purpose IO Register 1 bit 3
00514 #define    GPIOR14         4       // General Purpose IO Register 1 bit 4
00515 #define    GPIOR15         5       // General Purpose IO Register 1 bit 5
00516 #define    GPIOR16         6       // General Purpose IO Register 1 bit 6
00517 #define    GPIOR17         7       // General Purpose IO Register 1 bit 7
00518 
00519 /* GPIOR0 - General Purpose IO Register 0 */
00520 #define    GPIOR00         0       // General Purpose IO Register 0 bit 0
00521 #define    GPIOR01         1       // General Purpose IO Register 0 bit 1
00522 #define    GPIOR02         2       // General Purpose IO Register 0 bit 2
00523 #define    GPIOR03         3       // General Purpose IO Register 0 bit 3
00524 #define    GPIOR04         4       // General Purpose IO Register 0 bit 4
00525 #define    GPIOR05         5       // General Purpose IO Register 0 bit 5
00526 #define    GPIOR06         6       // General Purpose IO Register 0 bit 6
00527 #define    GPIOR07         7       // General Purpose IO Register 0 bit 7
00528 
00529 /* PRR1 - Power Reduction Register1 */
00530 #define    PRUSART1        0       // Power Reduction USART1
00531 #define    PRUSART2        1       // Power Reduction USART2
00532 #define    PRUSART3        2       // Power Reduction USART3
00533 #define    PRTIM3          3       // Power Reduction Timer/Counter3
00534 #define    PRTIM4          4       // Power Reduction Timer/Counter4
00535 #define    PRTIM5          5       // Power Reduction Timer/Counter5
00536 
00537 /* PRR0 - Power Reduction Register0 */
00538 #define    PRADC           0       // Power Reduction ADC
00539 #define    PRUSART0        1       // Power Reduction USART
00540 #define    PRSPI           2       // Power Reduction Serial Peripheral Interface
00541 #define    PRTIM1          3       // Power Reduction Timer/Counter1
00542 #define    PRTIM0          5       // Power Reduction Timer/Counter0
00543 #define    PRTIM2          6       // Power Reduction Timer/Counter2
00544 #define    PRTWI           7       // Power Reduction TWI
00545 
00546 
00547 /* ***** TWI ************************** */
00548 /* TWAMR - TWI (Slave) Address Mask Register */
00549 #define    TWAM0           1       // 
00550 #define    TWAMR0          TWAM0   // For compatibility
00551 #define    TWAM1           2       // 
00552 #define    TWAMR1          TWAM1   // For compatibility
00553 #define    TWAM2           3       // 
00554 #define    TWAMR2          TWAM2   // For compatibility
00555 #define    TWAM3           4       // 
00556 #define    TWAMR3          TWAM3   // For compatibility
00557 #define    TWAM4           5       // 
00558 #define    TWAMR4          TWAM4   // For compatibility
00559 #define    TWAM5           6       // 
00560 #define    TWAMR5          TWAM5   // For compatibility
00561 #define    TWAM6           7       // 
00562 #define    TWAMR6          TWAM6   // For compatibility
00563 
00564 /* TWBR - TWI Bit Rate register */
00565 #define    TWBR0           0       // 
00566 #define    TWBR1           1       // 
00567 #define    TWBR2           2       // 
00568 #define    TWBR3           3       // 
00569 #define    TWBR4           4       // 
00570 #define    TWBR5           5       // 
00571 #define    TWBR6           6       // 
00572 #define    TWBR7           7       // 
00573 
00574 /* TWCR - TWI Control Register */
00575 #define    TWIE            0       // TWI Interrupt Enable
00576 #define    TWEN            2       // TWI Enable Bit
00577 #define    TWWC            3       // TWI Write Collition Flag
00578 #define    TWSTO           4       // TWI Stop Condition Bit
00579 #define    TWSTA           5       // TWI Start Condition Bit
00580 #define    TWEA            6       // TWI Enable Acknowledge Bit
00581 #define    TWINT           7       // TWI Interrupt Flag
00582 
00583 /* TWSR - TWI Status Register */
00584 #define    TWPS0           0       // TWI Prescaler
00585 #define    TWPS1           1       // TWI Prescaler
00586 #define    TWS3            3       // TWI Status
00587 #define    TWS4            4       // TWI Status
00588 #define    TWS5            5       // TWI Status
00589 #define    TWS6            6       // TWI Status
00590 #define    TWS7            7       // TWI Status
00591 
00592 /* TWDR - TWI Data register */
00593 #define    TWD0            0       // TWI Data Register Bit 0
00594 #define    TWD1            1       // TWI Data Register Bit 1
00595 #define    TWD2            2       // TWI Data Register Bit 2
00596 #define    TWD3            3       // TWI Data Register Bit 3
00597 #define    TWD4            4       // TWI Data Register Bit 4
00598 #define    TWD5            5       // TWI Data Register Bit 5
00599 #define    TWD6            6       // TWI Data Register Bit 6
00600 #define    TWD7            7       // TWI Data Register Bit 7
00601 
00602 /* TWAR - TWI (Slave) Address register */
00603 #define    TWGCE           0       // TWI General Call Recognition Enable Bit
00604 #define    TWA0            1       // TWI (Slave) Address register Bit 0
00605 #define    TWA1            2       // TWI (Slave) Address register Bit 1
00606 #define    TWA2            3       // TWI (Slave) Address register Bit 2
00607 #define    TWA3            4       // TWI (Slave) Address register Bit 3
00608 #define    TWA4            5       // TWI (Slave) Address register Bit 4
00609 #define    TWA5            6       // TWI (Slave) Address register Bit 5
00610 #define    TWA6            7       // TWI (Slave) Address register Bit 6
00611 
00612 
00613 /* ***** SPI ************************** */
00614 /* SPDR - SPI Data Register */
00615 #define    SPDR0           0       // SPI Data Register bit 0
00616 #define    SPDR1           1       // SPI Data Register bit 1
00617 #define    SPDR2           2       // SPI Data Register bit 2
00618 #define    SPDR3           3       // SPI Data Register bit 3
00619 #define    SPDR4           4       // SPI Data Register bit 4
00620 #define    SPDR5           5       // SPI Data Register bit 5
00621 #define    SPDR6           6       // SPI Data Register bit 6
00622 #define    SPDR7           7       // SPI Data Register bit 7
00623 
00624 /* SPSR - SPI Status Register */
00625 #define    SPI2X           0       // Double SPI Speed Bit
00626 #define    WCOL            6       // Write Collision Flag
00627 #define    SPIF            7       // SPI Interrupt Flag
00628 
00629 /* SPCR - SPI Control Register */
00630 #define    SPR0            0       // SPI Clock Rate Select 0
00631 #define    SPR1            1       // SPI Clock Rate Select 1
00632 #define    CPHA            2       // Clock Phase
00633 #define    CPOL            3       // Clock polarity
00634 #define    MSTR            4       // Master/Slave Select
00635 #define    DORD            5       // Data Order
00636 #define    SPE             6       // SPI Enable
00637 #define    SPIE            7       // SPI Interrupt Enable
00638 
00639 
00640 /* ***** USART1 *********************** */
00641 /* UDR1 - USART I/O Data Register */
00642 #define    UDR1_0          0       // USART I/O Data Register bit 0
00643 #define    UDR1_1          1       // USART I/O Data Register bit 1
00644 #define    UDR1_2          2       // USART I/O Data Register bit 2
00645 #define    UDR1_3          3       // USART I/O Data Register bit 3
00646 #define    UDR1_4          4       // USART I/O Data Register bit 4
00647 #define    UDR1_5          5       // USART I/O Data Register bit 5
00648 #define    UDR1_6          6       // USART I/O Data Register bit 6
00649 #define    UDR1_7          7       // USART I/O Data Register bit 7
00650 
00651 /* UCSR1A - USART Control and Status Register A */
00652 #define    MPCM1           0       // Multi-processor Communication Mode
00653 #define    U2X1            1       // Double the USART transmission speed
00654 #define    UPE1            2       // Parity Error
00655 #define    DOR1            3       // Data overRun
00656 #define    FE1             4       // Framing Error
00657 #define    UDRE1           5       // USART Data Register Empty
00658 #define    TXC1            6       // USART Transmitt Complete
00659 #define    RXC1            7       // USART Receive Complete
00660 
00661 /* UCSR1B - USART Control and Status Register B */
00662 #define    TXB81           0       // Transmit Data Bit 8
00663 #define    RXB81           1       // Receive Data Bit 8
00664 #define    UCSZ12          2       // Character Size
00665 #define    TXEN1           3       // Transmitter Enable
00666 #define    RXEN1           4       // Receiver Enable
00667 #define    UDRIE1          5       // USART Data register Empty Interrupt Enable
00668 #define    TXCIE1          6       // TX Complete Interrupt Enable
00669 #define    RXCIE1          7       // RX Complete Interrupt Enable
00670 
00671 /* UCSR1C - USART Control and Status Register C */
00672 #define    UCPOL1          0       // Clock Polarity
00673 #define    UCSZ10          1       // Character Size
00674 #define    UCSZ11          2       // Character Size
00675 #define    USBS1           3       // Stop Bit Select
00676 #define    UPM10           4       // Parity Mode Bit 0
00677 #define    UPM11           5       // Parity Mode Bit 1
00678 #define    UMSEL10         6       // USART Mode Select
00679 #define    UMSEL11         7       // USART Mode Select
00680 
00681 
00682 /* ***** USB_DEVICE ******************* */
00683 /* UDCON -  */
00684 #define    DETACH          0       // 
00685 #define    RMWKUP          1       // 
00686 #define    LSM             2       // 
00687 
00688 /* UDINT -  */
00689 #define    SUSPI           0       // 
00690 #define    MSOFI           1       // 
00691 #define    SOFI            2       // 
00692 #define    EORSTI          3       // 
00693 #define    WAKEUPI         4       // 
00694 #define    EORSMI          5       // 
00695 #define    UPRSMI          6       // 
00696 
00697 /* UDIEN -  */
00698 #define    SUSPE           0       // 
00699 #define    MSOFE           1       // 
00700 #define    SOFE            2       // 
00701 #define    EORSTE          3       // 
00702 #define    WAKEUPE         4       // 
00703 #define    EORSME          5       // 
00704 #define    UPRSME          6       // 
00705 
00706 /* UDADDR -  */
00707 #define    UDADDR0         0       // 
00708 #define    UDADDR1         1       // 
00709 #define    UDADDR2         2       // 
00710 #define    UDADDR3         3       // 
00711 #define    UDADDR4         4       // 
00712 #define    UDADDR5         5       // 
00713 #define    UDADDR6         6       // 
00714 #define    ADDEN           7       // 
00715 
00716 /* UDFNUML -  */
00717 #define    UDFNUML_0       0       // 
00718 #define    UDFNUML_1       1       // 
00719 #define    UDFNUML_2       2       // 
00720 #define    UDFNUML_3       3       // 
00721 #define    UDFNUML_4       4       // 
00722 #define    UDFNUML_5       5       // 
00723 #define    UDFNUML_6       6       // 
00724 #define    UDFNUML_7       7       // 
00725 
00726 /* UDFNUMH -  */
00727 #define    UDFNUMH_0       0       // 
00728 #define    UDFNUMH_1       1       // 
00729 #define    UDFNUMH_2       2       // 
00730 
00731 /* UDMFN -  */
00732 #define    FNCERR          4       // 
00733 
00734 /* UEINTX -  */
00735 #define    TXINI           0       // 
00736 #define    STALLEDI        1       // 
00737 #define    RXOUTI          2       // 
00738 #define    RXSTPI          3       // 
00739 #define    NAKOUTI         4       // 
00740 #define    RWAL            5       // 
00741 #define    NAKINI          6       // 
00742 #define    FIFOCON         7       // 
00743 
00744 /* UENUM -  */
00745 #define    UENUM_0         0       // 
00746 #define    UENUM_1         1       // 
00747 #define    UENUM_2         2       // 
00748 
00749 /* UERST -  */
00750 #define    EPRST0          0       // 
00751 #define    EPRST1          1       // 
00752 #define    EPRST2          2       // 
00753 #define    EPRST3          3       // 
00754 #define    EPRST4          4       // 
00755 #define    EPRST5          5       // 
00756 #define    EPRST6          6       // 
00757 
00758 /* UECONX -  */
00759 #define    EPEN            0       // 
00760 #define    RSTDT           3       // 
00761 #define    STALLRQC        4       // 
00762 #define    STALLRQ         5       // 
00763 
00764 /* UECFG0X -  */
00765 #define    EPDIR           0       // 
00766 #define    NYETDIS         1       // 
00767 #define    AUTOSW          2       // 
00768 #define    ISOSW           3       // 
00769 #define    EPTYPE0         6       // 
00770 #define    EPTYPE1         7       // 
00771 
00772 /* UECFG1X -  */
00773 #define    ALLOC           1       // 
00774 #define    EPBK0           2       // 
00775 #define    EPBK1           3       // 
00776 #define    EPSIZE0         4       // 
00777 #define    EPSIZE1         5       // 
00778 #define    EPSIZE2         6       // 
00779 
00780 /* UESTA0X -  */
00781 #define    NBUSYBK0        0       // 
00782 #define    NBUSYBK1        1       // 
00783 #define    DTSEQ0          2       // 
00784 #define    DTSEQ1          3       // 
00785 #define    ZLPSEEN         4       // 
00786 #define    UNDERFI         5       // 
00787 #define    OVERFI          6       // 
00788 #define    CFGOK           7       // 
00789 
00790 /* UESTA1X -  */
00791 #define    CURRBK0         0       // 
00792 #define    CURRBK1         1       // 
00793 #define    CTRLDIR         2       // 
00794 
00795 /* UEIENX -  */
00796 #define    TXINE           0       // 
00797 #define    STALLEDE        1       // 
00798 #define    RXOUTE          2       // 
00799 #define    RXSTPE          3       // 
00800 #define    NAKOUTE         4       // 
00801 #define    NAKINE          6       // 
00802 #define    FLERRE          7       // 
00803 
00804 /* UEDATX -  */
00805 #define    UEDATX_0        0       // 
00806 #define    UEDATX_1        1       // 
00807 #define    UEDATX_2        2       // 
00808 #define    UEDATX_3        3       // 
00809 #define    UEDATX_4        4       // 
00810 #define    UEDATX_5        5       // 
00811 #define    UEDATX_6        6       // 
00812 #define    UEDATX_7        7       // 
00813 
00814 /* UEBCLX -  */
00815 #define    UEBCLX_0        0       // 
00816 #define    UEBCLX_1        1       // 
00817 #define    UEBCLX_2        2       // 
00818 #define    UEBCLX_3        3       // 
00819 #define    UEBCLX_4        4       // 
00820 #define    UEBCLX_5        5       // 
00821 #define    UEBCLX_6        6       // 
00822 #define    UEBCLX_7        7       // 
00823 
00824 /* UEBCHX -  */
00825 #define    UEBCHX_0        0       // 
00826 #define    UEBCHX_1        1       // 
00827 #define    UEBCHX_2        2       // 
00828 
00829 /* UEINT -  */
00830 #define    UEINT_0         0       // 
00831 #define    UEINT_1         1       // 
00832 #define    UEINT_2         2       // 
00833 #define    UEINT_3         3       // 
00834 #define    UEINT_4         4       // 
00835 #define    UEINT_5         5       // 
00836 #define    UEINT_6         6       // 
00837 
00838 
00839 /* ***** USB_GLOBAL ******************* */
00840 /* UHWCON - USB Hardware Configuration Register */
00841 #define    UVREGE          0       // 
00842 #define    UVCONE          4       // 
00843 #define    UIDE            6       // 
00844 #define    UIMOD           7       // 
00845 
00846 /* USBCON - USB General Control Register */
00847 #define    VBUSTE          0       // 
00848 #define    IDTE            1       // 
00849 #define    OTGPADE         4       // 
00850 #define    FRZCLK          5       // 
00851 #define    HOST            6       // 
00852 #define    USBE            7       // 
00853 
00854 /* USBSTA -  */
00855 #define    VBUS            0       // 
00856 #define    ID              1       // 
00857 #define    SPEED1          3       // 
00858 
00859 /* USBINT -  */
00860 #define    VBUSTI          0       // 
00861 #define    IDTI            1       // 
00862 
00863 /* OTGTCON -  */
00864 #define    OTGTCON_0       0       // 
00865 #define    OTGTCON_1       1       // 
00866 #define    OTGTCON_2       2       // 
00867 #define    OTGTCON_3       3       // 
00868 #define    OTGTCON_4       4       // 
00869 #define    OTGTCON_5       5       // 
00870 #define    OTGTCON_6       6       // 
00871 #define    OTGTCON_7       7       // 
00872 
00873 /* OTGCON -  */
00874 #define    VBUSRQC         0       // 
00875 #define    VBUSREQ         1       // 
00876 #define    VBUSHWC         2       // 
00877 #define    SRPSEL          3       // 
00878 #define    SRPREQ          4       // 
00879 #define    HNPREQ          5       // 
00880 
00881 /* OTGIEN -  */
00882 #define    SRPE            0       // 
00883 #define    VBERRE          1       // 
00884 #define    BCERRE          2       // 
00885 #define    ROLEEXE         3       // 
00886 #define    HNPERRE         4       // 
00887 #define    STOE            5       // 
00888 
00889 /* OTGINT -  */
00890 #define    SRPI            0       // 
00891 #define    VBERRI          1       // 
00892 #define    BCERRI          2       // 
00893 #define    ROLEEXI         3       // 
00894 #define    HNPERRI         4       // 
00895 #define    STOI            5       // 
00896 
00897 
00898 /* ***** USB_HOST ********************* */
00899 /* UHCON -  */
00900 #define    SOFEN           0       // 
00901 #define    RESET           1       // 
00902 #define    RESUME          2       // 
00903 
00904 /* UHINT -  */
00905 #define    DCONNI          0       // 
00906 #define    DDISCI          1       // 
00907 #define    RSTI            2       // 
00908 #define    RSMEDI          3       // 
00909 #define    RXRSMI          4       // 
00910 #define    HSOFI           5       // 
00911 #define    HWUPI           6       // 
00912 
00913 /* UHIEN -  */
00914 #define    HWUPE           6
00915 #define    HSOFE           5
00916 #define    RXRSME          4
00917 #define    RSMEDE          3
00918 #define    RSTE            2
00919 #define    DDISCE          1
00920 #define    DCONNE          0
00921 
00922 /* UHADDR -  */
00923 #define    UHADDR_0        0       // 
00924 #define    UHADDR_1        1       // 
00925 #define    UHADDR_2        2       // 
00926 #define    UHADDR_3        3       // 
00927 #define    UHADDR_4        4       // 
00928 #define    UHADDR_5        5       // 
00929 #define    UHADDR_6        6       // 
00930 
00931 /* UHFNUMH -  */
00932 #define    UHFNUMH_0       0       // 
00933 #define    UHFNUMH_1       1       // 
00934 #define    UHFNUMH_2       2       // 
00935 
00936 /* UHFNUML -  */
00937 #define    UHFNUML_0       0       // 
00938 #define    UHFNUML_1       1       // 
00939 #define    UHFNUML_2       2       // 
00940 #define    UHFNUML_3       3       // 
00941 #define    UHFNUML_4       4       // 
00942 #define    UHFNUML_5       5       // 
00943 #define    UHFNUML_6       6       // 
00944 #define    UHFNUML_7       7       // 
00945 
00946 /* UHFLEN -  */
00947 #define    UHFLEN_0        0       // 
00948 #define    UHFLEN_1        1       // 
00949 #define    UHFLEN_2        2       // 
00950 #define    UHFLEN_3        3       // 
00951 #define    UHFLEN_4        4       // 
00952 #define    UHFLEN_5        5       // 
00953 #define    UHFLEN_6        6       // 
00954 #define    UHFLEN_7        7       // 
00955 
00956 /* UPINRQX -  */
00957 #define    INRQ0           0       // 
00958 #define    INRQ1           1       // 
00959 #define    INRQ2           2       // 
00960 #define    INRQ3           3       // 
00961 #define    INRQ4           4       // 
00962 #define    INRQ5           5       // 
00963 #define    INRQ6           6       // 
00964 #define    INRQ7           7       // 
00965 
00966 /* UPINTX -  */
00967 #define    RXINI           0       // 
00968 #define    RXSTALLI        1       // 
00969 #define    TXOUTI          2       // 
00970 #define    TXSTPI          3       // 
00971 #define    PERRI           4       // 
00972 //#define  RWAL            5       // 
00973 #define    NAKEDI          6       // 
00974 //#define  FIFOCON         7       // 
00975 
00976 /* UPNUM -  */
00977 #define    PNUM0           0       // 
00978 #define    PNUM1           1       // 
00979 #define    PNUM2           2       // 
00980 
00981 /* UPRST -  */
00982 #define    PRST0           0       // 
00983 #define    PRST1           1       // 
00984 #define    PRST2           2       // 
00985 #define    PRST3           3       // 
00986 #define    PRST4           4       // 
00987 #define    PRST5           5       // 
00988 #define    PRST6           6       // 
00989 
00990 /* UPCONX -  */
00991 #define    PEN             0       // 
00992 //#define  RSTDT           3       // 
00993 #define    INMODE          5       // 
00994 #define    PFREEZE         6       // 
00995 
00996 /* UPCFG0X -  */
00997 #define    PEPNUM0         0       // 
00998 #define    PEPNUM1         1       // 
00999 #define    PEPNUM2         2       // 
01000 #define    PEPNUM3         3       // 
01001 #define    PTOKEN0         4       // 
01002 #define    PTOKEN1         5       // 
01003 #define    PTYPE0          6       // 
01004 #define    PTYPE1          7       // 
01005 
01006 /* UPCFG1X -  */
01007 //#define  ALLOC           1       // 
01008 #define    PBK0            2       // 
01009 #define    PBK1            3       // 
01010 #define    PSIZE0          4       // 
01011 #define    PSIZE1          5       // 
01012 #define    PSIZE2          6       // 
01013 
01014 /* UPSTAX -  */
01015 #define    NBUSYK0         0       // 
01016 #define    NBUSYK1         1       // 
01017 //#define  DTSEQ0          2       // 
01018 //#define  DTSEQ1          3       // 
01019 //#define  UNDERFI         5       // 
01020 //#define  OVERFI          6       // 
01021 //#define  CFGOK           7       // 
01022 
01023 /* UPCFG2X -  */
01024 #define    UPCFG2X_0       0       // 
01025 #define    UPCFG2X_1       1       // 
01026 #define    UPCFG2X_2       2       // 
01027 #define    UPCFG2X_3       3       // 
01028 #define    UPCFG2X_4       4       // 
01029 #define    UPCFG2X_5       5       // 
01030 #define    UPCFG2X_6       6       // 
01031 #define    UPCFG2X_7       7       // 
01032 
01033 /* UPIENX -  */
01034 #define    RXINE           0       // 
01035 #define    RXSTALLE        1       // 
01036 #define    TXOUTE          2       // 
01037 #define    TXSTPE          3       // 
01038 #define    PERRE           4       // 
01039 #define    NAKEDE          6       // 
01040 //#define  FLERRE          7       // 
01041 
01042 /* UPDATX -  */
01043 #define    PDAT0           0       // 
01044 #define    PDAT1           1       // 
01045 #define    PDAT2           2       // 
01046 #define    PDAT3           3       // 
01047 #define    PDAT4           4       // 
01048 #define    PDAT5           5       // 
01049 #define    PDAT6           6       // 
01050 #define    PDAT7           7       // 
01051 
01052 /* UPBCLX -  */
01053 #define    PBYCT0          0       // 
01054 #define    PBYCT1          1       // 
01055 #define    PBYCT2          2       // 
01056 #define    PBYCT3          3       // 
01057 #define    PBYCT4          4       // 
01058 #define    PBYCT5          5       // 
01059 #define    PBYCT6          6       // 
01060 #define    PBYCT7          7       // 
01061 
01062 /* UPBCHX -  */
01063 #define    PBYCT8          0       // 
01064 #define    PBYCT9          1       // 
01065 #define    PBYCT10         2       // 
01066 
01067 /* UPINT -  */
01068 #define    PINT0           0       // 
01069 #define    PINT1           1       // 
01070 #define    PINT2           2       // 
01071 #define    PINT3           3       // 
01072 #define    PINT4           4       // 
01073 #define    PINT5           5       // 
01074 #define    PINT6           6       // 
01075 
01076 /* UPERRX -  */
01077 #define    DATATGL         0       // 
01078 #define    DATAPID         1       // 
01079 #define    PID             2       // 
01080 #define    TIMEOUT         3       // 
01081 #define    CRC16           4       // 
01082 #define    COUNTER0        5       // 
01083 #define    COUNTER1        6       // 
01084 
01085 
01086 /* ***** BOOT_LOAD ******************** */
01087 /* SPMCSR - Store Program Memory Control Register */
01088 #define    SPMEN           0       // Store Program Memory Enable
01089 #define    PGERS           1       // Page Erase
01090 #define    PGWRT           2       // Page Write
01091 #define    BLBSET          3       // Boot Lock Bit Set
01092 #define    RWWSRE          4       // Read While Write section read enable
01093 #define    SIGRD           5       // Signature Row Read
01094 #define    RWWSB           6       // Read While Write Section Busy
01095 #define    SPMIE           7       // SPM Interrupt Enable
01096 
01097 
01098 /* ***** EEPROM *********************** */
01099 /* EEARH - EEPROM Address Register Low Byte */
01100 #define    EEAR8           0       // EEPROM Read/Write Access Bit 8
01101 #define    EEAR9           1       // EEPROM Read/Write Access Bit 9
01102 #define    EEAR10          2       // EEPROM Read/Write Access Bit 10
01103 #define    EEAR11          3       // EEPROM Read/Write Access Bit 11
01104 
01105 /* EEARL - EEPROM Address Register Low Byte */
01106 #define    EEAR0           0       // EEPROM Read/Write Access Bit 0
01107 #define    EEAR1           1       // EEPROM Read/Write Access Bit 1
01108 #define    EEAR2           2       // EEPROM Read/Write Access Bit 2
01109 #define    EEAR3           3       // EEPROM Read/Write Access Bit 3
01110 #define    EEAR4           4       // EEPROM Read/Write Access Bit 4
01111 #define    EEAR5           5       // EEPROM Read/Write Access Bit 5
01112 #define    EEAR6           6       // EEPROM Read/Write Access Bit 6
01113 #define    EEAR7           7       // EEPROM Read/Write Access Bit 7
01114 
01115 /* EEDR - EEPROM Data Register */
01116 #define    EEDR0           0       // EEPROM Data Register bit 0
01117 #define    EEDR1           1       // EEPROM Data Register bit 1
01118 #define    EEDR2           2       // EEPROM Data Register bit 2
01119 #define    EEDR3           3       // EEPROM Data Register bit 3
01120 #define    EEDR4           4       // EEPROM Data Register bit 4
01121 #define    EEDR5           5       // EEPROM Data Register bit 5
01122 #define    EEDR6           6       // EEPROM Data Register bit 6
01123 #define    EEDR7           7       // EEPROM Data Register bit 7
01124 
01125 /* EECR - EEPROM Control Register */
01126 #define    EERE            0       // EEPROM Read Enable
01127 #define    EEPE            1       // EEPROM Write Enable
01128 #define    EEMPE           2       // EEPROM Master Write Enable
01129 #define    EERIE           3       // EEPROM Ready Interrupt Enable
01130 #define    EEPM0           4       // EEPROM Programming Mode Bit 0
01131 #define    EEPM1           5       // EEPROM Programming Mode Bit 1
01132 
01133 
01134 /* ***** TIMER_COUNTER_0 ************** */
01135 /* TIMSK0 - Timer/Counter0 Interrupt Mask Register */
01136 #define    TOIE0           0       // Timer/Counter0 Overflow Interrupt Enable
01137 #define    OCIE0A          1       // Timer/Counter0 Output Compare Match A Interrupt Enable
01138 #define    OCIE0B          2       // Timer/Counter0 Output Compare Match B Interrupt Enable
01139 
01140 /* TIFR0 - Timer/Counter0 Interrupt Flag register */
01141 #define    TOV0            0       // Timer/Counter0 Overflow Flag
01142 #define    OCF0A           1       // Timer/Counter0 Output Compare Flag 0A
01143 #define    OCF0B           2       // Timer/Counter0 Output Compare Flag 0B
01144 
01145 /* TCCR0A - Timer/Counter  Control Register A */
01146 #define    WGM00           0       // Waveform Generation Mode
01147 #define    WGM01           1       // Waveform Generation Mode
01148 #define    COM0B0          4       // Compare Output Mode, Fast PWm
01149 #define    COM0B1          5       // Compare Output Mode, Fast PWm
01150 #define    COM0A0          6       // Compare Output Mode, Phase Correct PWM Mode
01151 #define    COM0A1          7       // Compare Output Mode, Phase Correct PWM Mode
01152 
01153 /* TCCR0B - Timer/Counter Control Register B */
01154 #define    CS00            0       // Clock Select
01155 #define    CS01            1       // Clock Select
01156 #define    CS02            2       // Clock Select
01157 #define    WGM02           3       // 
01158 #define    FOC0B           6       // Force Output Compare B
01159 #define    FOC0A           7       // Force Output Compare A
01160 
01161 /* TCNT0 - Timer/Counter0 */
01162 #define    TCNT0_0         0       // 
01163 #define    TCNT0_1         1       // 
01164 #define    TCNT0_2         2       // 
01165 #define    TCNT0_3         3       // 
01166 #define    TCNT0_4         4       // 
01167 #define    TCNT0_5         5       // 
01168 #define    TCNT0_6         6       // 
01169 #define    TCNT0_7         7       // 
01170 
01171 /* OCR0A - Timer/Counter0 Output Compare Register */
01172 #define    OCROA_0         0       // 
01173 #define    OCROA_1         1       // 
01174 #define    OCROA_2         2       // 
01175 #define    OCROA_3         3       // 
01176 #define    OCROA_4         4       // 
01177 #define    OCROA_5         5       // 
01178 #define    OCROA_6         6       // 
01179 #define    OCROA_7         7       // 
01180 
01181 /* OCR0B - Timer/Counter0 Output Compare Register */
01182 #define    OCR0B_0         0       // 
01183 #define    OCR0B_1         1       // 
01184 #define    OCR0B_2         2       // 
01185 #define    OCR0B_3         3       // 
01186 #define    OCR0B_4         4       // 
01187 #define    OCR0B_5         5       // 
01188 #define    OCR0B_6         6       // 
01189 #define    OCR0B_7         7       // 
01190 
01191 /* GTCCR - General Timer/Counter Control Register */
01192 #define    PSRSYNC         0       // Prescaler Reset Timer/Counter1 and Timer/Counter0
01193 #define    PSR10           PSRSYNC // For compatibility
01194 #define    TSM             7       // Timer/Counter Synchronization Mode
01195 
01196 
01197 /* ***** TIMER_COUNTER_2 ************** */
01198 /* TIMSK2 - Timer/Counter Interrupt Mask register */
01199 #define    TOIE2           0       // Timer/Counter2 Overflow Interrupt Enable
01200 #define    TOIE2A          TOIE2   // For compatibility
01201 #define    OCIE2A          1       // Timer/Counter2 Output Compare Match A Interrupt Enable
01202 #define    OCIE2B          2       // Timer/Counter2 Output Compare Match B Interrupt Enable
01203 
01204 /* TIFR2 - Timer/Counter Interrupt Flag Register */
01205 #define    TOV2            0       // Timer/Counter2 Overflow Flag
01206 #define    OCF2A           1       // Output Compare Flag 2A
01207 #define    OCF2B           2       // Output Compare Flag 2B
01208 
01209 /* TCCR2A - Timer/Counter2 Control Register A */
01210 #define    WGM20           0       // Waveform Genration Mode
01211 #define    WGM21           1       // Waveform Genration Mode
01212 #define    COM2B0          4       // Compare Output Mode bit 0
01213 #define    COM2B1          5       // Compare Output Mode bit 1
01214 #define    COM2A0          6       // Compare Output Mode bit 1
01215 #define    COM2A1          7       // Compare Output Mode bit 1
01216 
01217 /* TCCR2B - Timer/Counter2 Control Register B */
01218 #define    CS20            0       // Clock Select bit 0
01219 #define    CS21            1       // Clock Select bit 1
01220 #define    CS22            2       // Clock Select bit 2
01221 #define    WGM22           3       // Waveform Generation Mode
01222 #define    FOC2B           6       // Force Output Compare B
01223 #define    FOC2A           7       // Force Output Compare A
01224 
01225 /* TCNT2 - Timer/Counter2 */
01226 #define    TCNT2_0         0       // Timer/Counter 2 bit 0
01227 #define    TCNT2_1         1       // Timer/Counter 2 bit 1
01228 #define    TCNT2_2         2       // Timer/Counter 2 bit 2
01229 #define    TCNT2_3         3       // Timer/Counter 2 bit 3
01230 #define    TCNT2_4         4       // Timer/Counter 2 bit 4
01231 #define    TCNT2_5         5       // Timer/Counter 2 bit 5
01232 #define    TCNT2_6         6       // Timer/Counter 2 bit 6
01233 #define    TCNT2_7         7       // Timer/Counter 2 bit 7
01234 
01235 /* OCR2A - Timer/Counter2 Output Compare Register A */
01236 #define    OCR2_0          0       // Timer/Counter2 Output Compare Register Bit 0
01237 #define    OCR2_1          1       // Timer/Counter2 Output Compare Register Bit 1
01238 #define    OCR2_2          2       // Timer/Counter2 Output Compare Register Bit 2
01239 #define    OCR2_3          3       // Timer/Counter2 Output Compare Register Bit 3
01240 #define    OCR2_4          4       // Timer/Counter2 Output Compare Register Bit 4
01241 #define    OCR2_5          5       // Timer/Counter2 Output Compare Register Bit 5
01242 #define    OCR2_6          6       // Timer/Counter2 Output Compare Register Bit 6
01243 #define    OCR2_7          7       // Timer/Counter2 Output Compare Register Bit 7
01244 
01245 /* OCR2B - Timer/Counter2 Output Compare Register B */
01246 //#define  OCR2_0          0       // Timer/Counter2 Output Compare Register Bit 0
01247 //#define  OCR2_1          1       // Timer/Counter2 Output Compare Register Bit 1
01248 //#define  OCR2_2          2       // Timer/Counter2 Output Compare Register Bit 2
01249 //#define  OCR2_3          3       // Timer/Counter2 Output Compare Register Bit 3
01250 //#define  OCR2_4          4       // Timer/Counter2 Output Compare Register Bit 4
01251 //#define  OCR2_5          5       // Timer/Counter2 Output Compare Register Bit 5
01252 //#define  OCR2_6          6       // Timer/Counter2 Output Compare Register Bit 6
01253 //#define  OCR2_7          7       // Timer/Counter2 Output Compare Register Bit 7
01254 
01255 /* ASSR - Asynchronous Status Register */
01256 #define    TCR2BUB         0       // Timer/Counter Control Register2 Update Busy
01257 #define    TCR2AUB         1       // Timer/Counter Control Register2 Update Busy
01258 #define    OCR2BUB         2       // Output Compare Register 2 Update Busy
01259 #define    OCR2AUB         3       // Output Compare Register2 Update Busy
01260 #define    TCN2UB          4       // Timer/Counter2 Update Busy
01261 #define    AS2             5       // Asynchronous Timer/Counter2
01262 #define    EXCLK           6       // Enable External Clock Input
01263 
01264 /* GTCCR - General Timer Counter Control register */
01265 #define    PSRASY          1       // Prescaler Reset Timer/Counter2
01266 #define    PSR2            PSRASY  // For compatibility
01267 //#define  TSM             7       // Timer/Counter Synchronization Mode
01268 
01269 
01270 /* ***** TIMER_COUNTER_3 ************** */
01271 /* TIMSK3 - Timer/Counter3 Interrupt Mask Register */
01272 #define    TOIE3           0       // Timer/Counter3 Overflow Interrupt Enable
01273 #define    OCIE3A          1       // Timer/Counter3 Output Compare A Match Interrupt Enable
01274 #define    OCIE3B          2       // Timer/Counter3 Output Compare B Match Interrupt Enable
01275 #define    OCIE3C          3       // Timer/Counter3 Output Compare C Match Interrupt Enable
01276 #define    ICIE3           5       // Timer/Counter3 Input Capture Interrupt Enable
01277 
01278 /* TIFR3 - Timer/Counter3 Interrupt Flag register */
01279 #define    TOV3            0       // Timer/Counter3 Overflow Flag
01280 #define    OCF3A           1       // Output Compare Flag 3A
01281 #define    OCF3B           2       // Output Compare Flag 3B
01282 #define    OCF3C           3       // Output Compare Flag 3C
01283 #define    ICF3            5       // Input Capture Flag 3
01284 
01285 /* TCCR3A - Timer/Counter3 Control Register A */
01286 #define    WGM30           0       // Waveform Generation Mode
01287 #define    WGM31           1       // Waveform Generation Mode
01288 #define    COM3C0          2       // Compare Output Mode 3C, bit 0
01289 #define    COM3C1          3       // Compare Output Mode 3C, bit 1
01290 #define    COM3B0          4       // Compare Output Mode 3B, bit 0
01291 #define    COM3B1          5       // Compare Output Mode 3B, bit 1
01292 #define    COM3A0          6       // Compare Output Mode 3A, bit 0
01293 #define    COM3A1          7       // Compare Output Mode 1A, bit 1
01294 
01295 /* TCCR3B - Timer/Counter3 Control Register B */
01296 #define    CS30            0       // Prescaler source of Timer/Counter 3
01297 #define    CS31            1       // Prescaler source of Timer/Counter 3
01298 #define    CS32            2       // Prescaler source of Timer/Counter 3
01299 #define    WGM32           3       // Waveform Generation Mode
01300 #define    WGM33           4       // Waveform Generation Mode
01301 #define    ICES3           6       // Input Capture 3 Edge Select
01302 #define    ICNC3           7       // Input Capture 3 Noise Canceler
01303 
01304 /* TCCR3C - Timer/Counter 3 Control Register C */
01305 #define    FOC3C           5       // Force Output Compare 3C
01306 #define    FOC3B           6       // Force Output Compare 3B
01307 #define    FOC3A           7       // Force Output Compare 3A
01308 
01309 
01310 /* ***** TIMER_COUNTER_1 ************** */
01311 /* TIMSK1 - Timer/Counter1 Interrupt Mask Register */
01312 #define    TOIE1           0       // Timer/Counter1 Overflow Interrupt Enable
01313 #define    OCIE1A          1       // Timer/Counter1 Output Compare A Match Interrupt Enable
01314 #define    OCIE1B          2       // Timer/Counter1 Output Compare B Match Interrupt Enable
01315 #define    OCIE1C          3       // Timer/Counter1 Output Compare C Match Interrupt Enable
01316 #define    ICIE1           5       // Timer/Counter1 Input Capture Interrupt Enable
01317 
01318 /* TIFR1 - Timer/Counter1 Interrupt Flag register */
01319 #define    TOV1            0       // Timer/Counter1 Overflow Flag
01320 #define    OCF1A           1       // Output Compare Flag 1A
01321 #define    OCF1B           2       // Output Compare Flag 1B
01322 #define    OCF1C           3       // Output Compare Flag 1C
01323 #define    ICF1            5       // Input Capture Flag 1
01324 
01325 /* TCCR1A - Timer/Counter1 Control Register A */
01326 #define    WGM10           0       // Waveform Generation Mode
01327 #define    WGM11           1       // Waveform Generation Mode
01328 #define    COM1C0          2       // Compare Output Mode 1C, bit 0
01329 #define    COM1C1          3       // Compare Output Mode 1C, bit 1
01330 #define    COM1B0          4       // Compare Output Mode 1B, bit 0
01331 #define    COM1B1          5       // Compare Output Mode 1B, bit 1
01332 #define    COM1A0          6       // Compare Output Mode 1A, bit 0
01333 #define    COM1A1          7       // Compare Output Mode 1A, bit 1
01334 
01335 /* TCCR1B - Timer/Counter1 Control Register B */
01336 #define    CS10            0       // Prescaler source of Timer/Counter 1
01337 #define    CS11            1       // Prescaler source of Timer/Counter 1
01338 #define    CS12            2       // Prescaler source of Timer/Counter 1
01339 #define    WGM12           3       // Waveform Generation Mode
01340 #define    WGM13           4       // Waveform Generation Mode
01341 #define    ICES1           6       // Input Capture 1 Edge Select
01342 #define    ICNC1           7       // Input Capture 1 Noise Canceler
01343 
01344 /* TCCR1C - Timer/Counter 1 Control Register C */
01345 #define    FOC1C           5       // Force Output Compare 1C
01346 #define    FOC1B           6       // Force Output Compare 1B
01347 #define    FOC1A           7       // Force Output Compare 1A
01348 
01349 
01350 /* ***** JTAG ************************* */
01351 /* OCDR - On-Chip Debug Related Register in I/O Memory */
01352 #define    OCDR0           0       // On-Chip Debug Register Bit 0
01353 #define    OCDR1           1       // On-Chip Debug Register Bit 1
01354 #define    OCDR2           2       // On-Chip Debug Register Bit 2
01355 #define    OCDR3           3       // On-Chip Debug Register Bit 3
01356 #define    OCDR4           4       // On-Chip Debug Register Bit 4
01357 #define    OCDR5           5       // On-Chip Debug Register Bit 5
01358 #define    OCDR6           6       // On-Chip Debug Register Bit 6
01359 #define    OCDR7           7       // On-Chip Debug Register Bit 7
01360 #define    IDRD            OCDR7   // For compatibility
01361 
01362 /* MCUCR - MCU Control Register */
01363 //#define  JTD             7       // JTAG Interface Disable
01364 
01365 /* MCUSR - MCU Status Register */
01366 //#define  JTRF            4       // JTAG Reset Flag
01367 
01368 
01369 /* ***** EXTERNAL_INTERRUPT *********** */
01370 /* EICRA - External Interrupt Control Register A */
01371 #define    ISC00           0       // External Interrupt Sense Control Bit
01372 #define    ISC01           1       // External Interrupt Sense Control Bit
01373 #define    ISC10           2       // External Interrupt Sense Control Bit
01374 #define    ISC11           3       // External Interrupt Sense Control Bit
01375 #define    ISC20           4       // External Interrupt Sense Control Bit
01376 #define    ISC21           5       // External Interrupt Sense Control Bit
01377 #define    ISC30           6       // External Interrupt Sense Control Bit
01378 #define    ISC31           7       // External Interrupt Sense Control Bit
01379 
01380 /* EICRB - External Interrupt Control Register B */
01381 #define    ISC40           0       // External Interrupt 7-4 Sense Control Bit
01382 #define    ISC41           1       // External Interrupt 7-4 Sense Control Bit
01383 #define    ISC50           2       // External Interrupt 7-4 Sense Control Bit
01384 #define    ISC51           3       // External Interrupt 7-4 Sense Control Bit
01385 #define    ISC60           4       // External Interrupt 7-4 Sense Control Bit
01386 #define    ISC61           5       // External Interrupt 7-4 Sense Control Bit
01387 #define    ISC70           6       // External Interrupt 7-4 Sense Control Bit
01388 #define    ISC71           7       // External Interrupt 7-4 Sense Control Bit
01389 
01390 /* EIMSK - External Interrupt Mask Register */
01391 #define    INT0            0       // External Interrupt Request 0 Enable
01392 #define    INT1            1       // External Interrupt Request 1 Enable
01393 #define    INT2            2       // External Interrupt Request 2 Enable
01394 #define    INT3            3       // External Interrupt Request 3 Enable
01395 #define    INT4            4       // External Interrupt Request 4 Enable
01396 #define    INT5            5       // External Interrupt Request 5 Enable
01397 #define    INT6            6       // External Interrupt Request 6 Enable
01398 #define    INT7            7       // External Interrupt Request 7 Enable
01399 
01400 /* EIFR - External Interrupt Flag Register */
01401 #define    INTF0           0       // External Interrupt Flag 0
01402 #define    INTF1           1       // External Interrupt Flag 1
01403 #define    INTF2           2       // External Interrupt Flag 2
01404 #define    INTF3           3       // External Interrupt Flag 3
01405 #define    INTF4           4       // External Interrupt Flag 4
01406 #define    INTF5           5       // External Interrupt Flag 5
01407 #define    INTF6           6       // External Interrupt Flag 6
01408 #define    INTF7           7       // External Interrupt Flag 7
01409 
01410 /* PCICR - Pin Change Interrupt Control Register */
01411 #define    PCIE0           0       // Pin Change Interrupt Enable 0
01412 #define    PCIE1           1       // Pin Change Interrupt Enable 1
01413 #define    PCIE2           2       // Pin Change Interrupt Enable 2
01414 
01415 /* PCIFR - Pin Change Interrupt Flag Register */
01416 #define    PCIF0           0       // Pin Change Interrupt Flag 0
01417 #define    PCIF1           1       // Pin Change Interrupt Flag 1
01418 #define    PCIF2           2       // Pin Change Interrupt Flag 2
01419 
01420 /* PCMSK0 - Pin Change Mask Register 0 */
01421 #define    PCINT0          0       // Pin Change Enable Mask 0
01422 #define    PCINT1          1       // Pin Change Enable Mask 1
01423 #define    PCINT2          2       // Pin Change Enable Mask 2
01424 #define    PCINT3          3       // Pin Change Enable Mask 3
01425 #define    PCINT4          4       // Pin Change Enable Mask 4
01426 #define    PCINT5          5       // Pin Change Enable Mask 5
01427 #define    PCINT6          6       // Pin Change Enable Mask 6
01428 #define    PCINT7          7       // Pin Change Enable Mask 7
01429 
01430 
01431 /* ***** AD_CONVERTER ***************** */
01432 /* ADMUX - The ADC multiplexer Selection Register */
01433 #define    MUX0            0       // Analog Channel and Gain Selection Bits
01434 #define    MUX1            1       // Analog Channel and Gain Selection Bits
01435 #define    MUX2            2       // Analog Channel and Gain Selection Bits
01436 #define    MUX3            3       // Analog Channel and Gain Selection Bits
01437 #define    MUX4            4       // Analog Channel and Gain Selection Bits
01438 #define    ADLAR           5       // Left Adjust Result
01439 #define    REFS0           6       // Reference Selection Bit 0
01440 #define    REFS1           7       // Reference Selection Bit 1
01441 
01442 /* ADCSRA - The ADC Control and Status register */
01443 #define    ADPS0           0       // ADC  Prescaler Select Bits
01444 #define    ADPS1           1       // ADC  Prescaler Select Bits
01445 #define    ADPS2           2       // ADC  Prescaler Select Bits
01446 #define    ADIE            3       // ADC Interrupt Enable
01447 #define    ADIF            4       // ADC Interrupt Flag
01448 #define    ADATE           5       // ADC Auto Trigger Enable
01449 #define    ADSC            6       // ADC Start Conversion
01450 #define    ADEN            7       // ADC Enable
01451 
01452 /* ADCH - ADC Data Register High Byte */
01453 #define    ADCH0           0       // ADC Data Register High Byte Bit 0
01454 #define    ADCH1           1       // ADC Data Register High Byte Bit 1
01455 #define    ADCH2           2       // ADC Data Register High Byte Bit 2
01456 #define    ADCH3           3       // ADC Data Register High Byte Bit 3
01457 #define    ADCH4           4       // ADC Data Register High Byte Bit 4
01458 #define    ADCH5           5       // ADC Data Register High Byte Bit 5
01459 #define    ADCH6           6       // ADC Data Register High Byte Bit 6
01460 #define    ADCH7           7       // ADC Data Register High Byte Bit 7
01461 
01462 /* ADCL - ADC Data Register Low Byte */
01463 #define    ADCL0           0       // ADC Data Register Low Byte Bit 0
01464 #define    ADCL1           1       // ADC Data Register Low Byte Bit 1
01465 #define    ADCL2           2       // ADC Data Register Low Byte Bit 2
01466 #define    ADCL3           3       // ADC Data Register Low Byte Bit 3
01467 #define    ADCL4           4       // ADC Data Register Low Byte Bit 4
01468 #define    ADCL5           5       // ADC Data Register Low Byte Bit 5
01469 #define    ADCL6           6       // ADC Data Register Low Byte Bit 6
01470 #define    ADCL7           7       // ADC Data Register Low Byte Bit 7
01471 
01472 /* ADCSRB - ADC Control and Status Register B */
01473 #define    ADTS0           0       // ADC Auto Trigger Source 0
01474 #define    ADTS1           1       // ADC Auto Trigger Source 1
01475 #define    ADTS2           2       // ADC Auto Trigger Source 2
01476 #define    ADHSM           7       // ADC High Speed Mode
01477 
01478 /* DIDR0 - Digital Input Disable Register 1 */
01479 #define    ADC0D           0       // ADC0 Digital input Disable
01480 #define    ADC1D           1       // ADC1 Digital input Disable
01481 #define    ADC2D           2       // ADC2 Digital input Disable
01482 #define    ADC3D           3       // ADC3 Digital input Disable
01483 #define    ADC4D           4       // ADC4 Digital input Disable
01484 #define    ADC5D           5       // ADC5 Digital input Disable
01485 #define    ADC6D           6       // ADC6 Digital input Disable
01486 #define    ADC7D           7       // ADC7 Digital input Disable
01487 
01488 
01489 /* ***** ANALOG_COMPARATOR ************ */
01490 /* ADCSRB - ADC Control and Status Register B */
01491 #define    ACME            6       // Analog Comparator Multiplexer Enable
01492 
01493 /* ACSR - Analog Comparator Control And Status Register */
01494 #define    ACIS0           0       // Analog Comparator Interrupt Mode Select bit 0
01495 #define    ACIS1           1       // Analog Comparator Interrupt Mode Select bit 1
01496 #define    ACIC            2       // Analog Comparator Input Capture Enable
01497 #define    ACIE            3       // Analog Comparator Interrupt Enable
01498 #define    ACI             4       // Analog Comparator Interrupt Flag
01499 #define    ACO             5       // Analog Compare Output
01500 #define    ACBG            6       // Analog Comparator Bandgap Select
01501 #define    ACD             7       // Analog Comparator Disable
01502 
01503 /* DIDR1 -  */
01504 #define    AIN0D           0       // AIN0 Digital Input Disable
01505 #define    AIN1D           1       // AIN1 Digital Input Disable
01506 
01507 
01508 /* ***** PLL ************************** */
01509 /* PLLCSR - PLL Status and Control register */
01510 #define    PLOCK           0       // PLL Lock Status Bit
01511 #define    PLLE            1       // PLL Enable Bit
01512 #define    PLLP0           2       // PLL prescaler Bit 0
01513 #define    PLLP1           3       // PLL prescaler Bit 1
01514 #define    PLLP2           4       // PLL prescaler Bit 2
01515 
01516 
01517 
01518 /* ***** LOCKSBITS ******************************************************** */
01519 #define    LB1             0       // Lock bit
01520 #define    LB2             1       // Lock bit
01521 #define    BLB01           2       // Boot Lock bit
01522 #define    BLB02           3       // Boot Lock bit
01523 #define    BLB11           4       // Boot lock bit
01524 #define    BLB12           5       // Boot lock bit
01525 
01526 
01527 /* ***** FUSES ************************************************************ */
01528 /* LOW fuse bits */
01529 #define    CKSEL0          0       // Select Clock Source
01530 #define    CKSEL1          1       // Select Clock Source
01531 #define    CKSEL2          2       // Select Clock Source
01532 #define    CKSEL3          3       // Select Clock Source
01533 #define    SUT0            4       // Select start-up time
01534 #define    SUT1            5       // Select start-up time
01535 #define    CKOUT           6       // Oscillator options
01536 #define    CLKDIV8         7       // Divide clock by 8
01537 
01538 /* HIGH fuse bits */
01539 #define    BOOTRST         0       // Select Reset Vector
01540 #define    BOOTSZ0         1       // Select Boot Size
01541 #define    BOOTSZ1         2       // Select Boot Size
01542 #define    EESAVE          3       // EEPROM memory is preserved through chip erase
01543 #define    WDTON           4       // Watchdog timer always on
01544 #define    SPIEN           5       // Enable Serial programming and Data Downloading
01545 #define    JTAGEN          6       // Enable JTAG
01546 #define    OCDEN           7       // Enable OCD
01547 
01548 /* EXTENDED fuse bits */
01549 #define    BODLEVEL0       0       // Brown-out Detector trigger level
01550 #define    BODLEVEL1       1       // Brown-out Detector trigger level
01551 #define    BODLEVEL2       2       // Brown-out Detector trigger level
01552 #define    HWBE            3       // Hardware Boot Enable
01553 
01554 
01555 
01556 /* ***** CPU REGISTER DEFINITIONS ***************************************** */
01557 #define    XH              r27
01558 #define    XL              r26
01559 #define    YH              r29
01560 #define    YL              r28
01561 #define    ZH              r31
01562 #define    ZL              r30
01563 
01564 
01565 
01566 /* ***** DATA MEMORY DECLARATIONS ***************************************** */
01567 #define    FLASHEND        0x1ffff // Note: Byte address
01568 #define    IOEND           0x00ff
01569 #define    SRAM_START      0x0100
01570 #define    SRAM_SIZE       8192
01571 #define    RAMEND          0x20ff
01572 #define    XRAMEND         0xffff
01573 #define    E2END           0x0fff
01574 #define    EEPROMEND       0x0fff
01575 #define    EEADRBITS       12
01576 
01577 
01578 
01579 /* ***** BOOTLOADER DECLARATIONS ****************************************** */
01580 #define    NRWW_START_ADDR 0xf000
01581 #define    NRWW_STOP_ADDR  0xffff
01582 #define    RWW_START_ADDR  0x0
01583 #define    RWW_STOP_ADDR   0xefff
01584 #define    PAGESIZE        128
01585 #define    FIRSTBOOTSTART  0xfe00
01586 #define    SECONDBOOTSTART 0xfc00
01587 #define    THIRDBOOTSTART  0xf800
01588 #define    FOURTHBOOTSTART 0xf000
01589 #define    SMALLBOOTSTART  FIRSTBOOTSTART
01590 #define    LARGEBOOTSTART  FOURTHBOOTSTART
01591 
01592 
01593 
01594 /* ***** INTERRUPT VECTORS ************************************************ */
01595 #define    SIG_INTERRUPT0  _VECTOR(1) // External Interrupt Request 0
01596 #define    SIG_INTERRUPT1  _VECTOR(2) // External Interrupt Request 1
01597 #define    SIG_INTERRUPT2  _VECTOR(3) // External Interrupt Request 2
01598 #define    SIG_INTERRUPT3  _VECTOR(4) // External Interrupt Request 3
01599 #define    SIG_INTERRUPT4  _VECTOR(5) // External Interrupt Request 4
01600 #define    SIG_INTERRUPT5  _VECTOR(6) // External Interrupt Request 5
01601 #define    SIG_INTERRUPT6  _VECTOR(7) // External Interrupt Request 6
01602 #define    SIG_INTERRUPT7  _VECTOR(8) // External Interrupt Request 7
01603 #define    SIG_PIN_CHANGE0 _VECTOR(9) // Pin Change Interrupt Request 0
01604 #define    SIG_USB_GEN     _VECTOR(10) // USB General Interrupt Request
01605 #define    SIG_USB_COM     _VECTOR(11) // USB Endpoint/Pipe Interrupt Communication Request
01606 #define    SIG_WDT         _VECTOR(12) // Watchdog Time-out Interrupt
01607 #define    SIG_OUTPUT_COMPARE2A _VECTOR(13) // Timer/Counter2 Compare Match A
01608 #define    SIG_OUTPUT_COMPARE2B _VECTOR(14) // Timer/Counter2 Compare Match B
01609 #define    SIG_OVERFLOW2   _VECTOR(15) // Timer/Counter2 Overflow
01610 #define    SIG_INPUT_CAPTURE1 _VECTOR(16) // Timer/Counter1 Capture Event
01611 #define    SIG_OUTPUT_COMPARE1A _VECTOR(17) // Timer/Counter1 Compare Match A
01612 #define    SIG_OUTPUT_COMPARE1B _VECTOR(18) // Timer/Counter1 Compare Match B
01613 #define    SIG_OUTPUT_COMPARE1C _VECTOR(19) // Timer/Counter1 Compare Match C
01614 #define    SIG_OVERFLOW1   _VECTOR(20) // Timer/Counter1 Overflow
01615 #define    SIG_OUTPUT_COMPARE0A _VECTOR(21) // Timer/Counter0 Compare Match A
01616 #define    SIG_OUTPUT_COMPARE0B _VECTOR(22) // Timer/Counter0 Compare Match B
01617 #define    SIG_OVERFLOW0   _VECTOR(23) // Timer/Counter0 Overflow
01618 #define    SIG_SPI         _VECTOR(24) // SPI Serial Transfer Complete
01619 #define    SIG_USART1_RECV _VECTOR(25) // USART1, Rx Complete
01620 #define    SIG_USART1_DATA _VECTOR(26) // USART1 Data register Empty
01621 #define    SIG_USART1_TRANS _VECTOR(27) // USART1, Tx Complete
01622 #define    SIG_COMPARATOR  _VECTOR(28) // Analog Comparator
01623 #define    SIG_ADC         _VECTOR(29) // ADC Conversion Complete
01624 #define    SIG_EEPROM_READY _VECTOR(30) // EEPROM Ready
01625 #define    SIG_INPUT_CAPTURE3 _VECTOR(31) // Timer/Counter3 Capture Event
01626 #define    SIG_OUTPUT_COMPARE3A _VECTOR(32) // Timer/Counter3 Compare Match A
01627 #define    SIG_OUTPUT_COMPARE3B _VECTOR(33) // Timer/Counter3 Compare Match B
01628 #define    SIG_OUTPUT_COMPARE3C _VECTOR(34) // Timer/Counter3 Compare Match C
01629 #define    SIG_OVERFLOW3   _VECTOR(35) // Timer/Counter3 Overflow
01630 #define    SIG_2WIRE_SERIAL _VECTOR(36) // 2-wire Serial Interface
01631 #define    SIG_SPM_READY   _VECTOR(37) // Store Program Memory Read
01632 
01633 #define    _VECTORS_SIZE   152     // size in bytes
01634 
01635 #endif  /* _AVR_IOAT90USB1287_H_ */
01636 
01637 /* ***** END OF FILE ****************************************************** */

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