Port for FR family CPU core (Fujitsu)

Cross Core Softune Workbench V6


General

FR family CPU core (FR30, FR50 and next generations) has a 32-bit general-purpose register architecture with improved numeric implementation whereby a wide range of delayed branch instructions reduces losses in execution time due to pipeline breaks.

Context size is large enough and comes to about 80 bytes:

15 (R0 - R14) + 2 (MDL, MDH) + 1 (RP) + 1 (PC) + 1 (PS) = 20 32-bit registers
or 20*4 = 80 bytes.

but because efficient architecture context switch is quite fast - control flow passes from one process to another in about 10 us at 32 MHz core clock.

The FR microcontroller family have the two stacks pointers, user(USP) and system(SSP). The port works with both of stacks. When you uses both stacks in the system, all interrupts and OS's context switch function uses System Stack, and the OS's tasks are uses User Stack. In this case, the time of context switch is more than when only the system stack is used because some time for reload CPU program counter(PC) and status(PS) from system stack to user stack in interrupts is needed. But due to this stack switch stack size of each task can be reduced because there is no need to reserve memory in each stack for processing the interrupts. It may be useful for "one-chip" systems without external RAM.

In startup.asm user should switch OFF user's stack usage. This leads that user's stack will be used only after start the task. Initializing the system will be done with use of the system stack, and user's stack usage begin after OS::Run().

The Port uses one common stack for data and return addresses.


Program Control Flow Transfer

One method - software interrupt - is supported in the port. This is because FR processor has native Software Interrupt that is very suitable for implementation of context switch.


Interrupts

The using of interrupts with scmRTOS does not make any special demands. The user should keep in mind two things:

  • interrupt service routine (ISR) function must be qualified with OS_INTERRUPT macro;
  • TISRW object must be declared at the beginning of the ISR. This object involves constructor and destructor that play very important role in the RTOS rescheduling mechanism and integrity. Switching to separate ISR stack is not implemented in current version of the port.

System Timer

FR microcontroller's Time Base Timer is used as System Timer hardware implementation. Setting up of the Time Base Timer must be carried out by the user's project code before the RTOS start.


Summary

See Release info for more details about port features and using examples.

As usual, see User's Manual for more details about RTOS contents, structure, functionality and features.