Сообщение от neyvert
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Запись ноля в этот регистр ничего не дает!
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Да, но этим TIM4-›SR &= ~TIM_SR_UIF; в SR пишется тоже ноль, только в один нулевой бит.
RM0316, rev.2, стр.500:
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
At overflow or underflow (for TIM2 to TIM4) and if UDIS=0 in the TIMx_CR1 register.
When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and
UDIS=0 in the TIMx_CR1 register.
When CNT is reinitialized by a trigger event (refer to the synchro control register description),
if URS=0 and UDIS=0 in the TIMx_CR1 register.